P-channel enhancement mode semiconductor device and method for manufacturing the same
AssigneeInnoscience (Suzhou) Technology Co., Ltd.
InventorsRonghui Hao, Fu Chen, King Yuen Wong
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Abstract
A semiconductor device includes a first and a second nitride-based semiconductor layers, a source electrode, a drain electrode, a passivation layer, a stress modulation layer and a gate electrode. The stress modulation layer is disposed over the second nitride-based semiconductor layer and extends along at least one sidewall of the passivation layer to make contact with the second nitride-based semiconductor layer, so as to form an interface. The gate electrode is disposed over the stress modulation layer and between the source and drain electrodes. The gate electrode is located directly above the interface of the stress modulation layer and the second nitride-based semiconductor layer.
Claims20
A semiconductor device comprising:
- a first nitride-based semiconductor layer;
- a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap less than a bandgap of the first nitride-based semiconductor layer to form a heterojunction therebetween with a two dimensional hole gas (2DHG) region;
- a source electrode and a drain electrode disposed over the second nitride-based semiconductor layer;
- a passivation layer disposed over the second nitride-based semiconductor layer and between the source and drain electrodes;
- a stress modulation layer disposed over the second nitride-based semiconductor layer and extending along at least one sidewall of the passivation layer to make contact with the second nitride-based semiconductor layer, so as to form an interface, wherein the stress modulation layer extends from a top surface of the passivation layer;
- and
- a gate electrode disposed over the stress modulation layer and between the source and drain electrodes, wherein the gate electrode is located directly above the interface between the stress modulation layer and the second nitride-based semiconductor layer.
A method for manufacturing a semiconductor device, comprising:
- forming a first nitride-based semiconductor layer;
- forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer to form a heterojunction therebetween with a two dimensional hole gas (2DHG) region;
- forming a source electrode and a drain electrode above the second nitride-based semiconductor layer;
- forming a passivation layer above the second nitride-based semiconductor layer;
- removing a portion of the passivation layer to form an opening exposing the second nitride-based semiconductor layer;
- forming a stress modulation layer above the passivation layer and filling into the opening to make contact with the second nitride-based semiconductor layer, wherein the stress modulation layer extends from a top surface of the passivation layer;
- and
- forming a gate electrode above the stress modulation layer and aligning with the opening.
A semiconductor device comprising:
- a first nitride-based semiconductor layer;
- a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap less than a bandgap of the first nitride-based semiconductor layer to form a heterojunction therebetween with a two dimensional hole gas (2DHG) region;
- a source electrode and a drain electrode disposed over the second nitride-based semiconductor layer;
- a passivation layer disposed over the second nitride-based semiconductor layer and between the source and drain electrodes;
- a stress modulation layer disposed over the second nitride-based semiconductor layer and extending along at least one sidewall of the passivation layer to make contact with the second nitride-based semiconductor layer, so as to form an interface, wherein the stress modulation layer has a first portion above a top surface of the passivation layer and a second portion in contact with the second nitride-based semiconductor layer and connected to the first portion;
- and
- a gate electrode disposed over the stress modulation layer and between the source and drain electrodes, wherein the gate electrode is located directly above the interface between the stress modulation layer and the second nitride-based semiconductor layer.
Dependencies are inferred from the claim text.