Three-dimensional circuits with flexible interconnects
AssigneeDujud LLC
InventorReza Abbaspour
Life of this patent
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Abstract
Three-dimensional (3D) devices that include at least two electrically isolated planes of electrically conductive traces and methods of making the same. The 3D device includes an upper level, a lower level electrically isolated from the upper level, and one or more pedestal portions joining the upper level and the lower level. The pedestal portions comprise an undercut. The undercut defines an upper level overhang that is configured to define a mask region to prevent conductive material from being deposited below the undercut.
Claims20
A three-dimensional (3D) electronic circuit, comprising:
- at least two electrically isolated planes of electrically conductive traces formed by deposition of a selected material on a 3D structure formed by an additive polymer photocuring process, the 3D structure comprising:
- an upper level comprising a first set of the electrically conductive traces;
- a lower level comprising a second set of the electrically conductive traces that are electrically isolated from the electrically conductive traces of the upper level;
- and
- a pedestal portion directly joining the upper level and the lower level, the pedestal portions comprising an undercut;
- wherein the first set of the electrically conductive traces at the upper level, the pedestal portion, and the second set of the electrically conductive traces at the lower level form the 3D electronic circuit.
A method of additively manufacturing a three-dimensional (3D) electronic circuit device structure, the method comprising:
- additively forming and photocuring a 3D structure, the 3D structure is characterized by:
- one or more three-dimensional flexible interconnects (3FIs);
- an upper level comprising a first set of electrically conductive traces;
- a lower level comprising a second set of electrically conductive traces that are electrically isolated from the first set of electrically conductive traces of the upper level;
- and
- a pedestal portion directly joining the upper level and the lower level, the pedestal portion comprising an undercut, wherein the undercut defines an upper level overhang configured to define a mask region over a portion of the lower level;
- and
- forming at least two electrically isolated planes of electronic circuitry by directionally depositing a selected material on the one or more 3FIs, the upper level, and one or more non-masked portions of the lower level, wherein the first set of the electrically conductive traces at the upper level, the pedestal portion, and the second set of the electrically conductive traces at the lower level form the 3D electronic circuit.
Dependencies are inferred from the claim text.