Method and an apparatus for generating an output clock in a multi-loop PLL system

A method for generating an output clock signal using multi-loop clock signal generator, the method comprising:

• generating, by a first phase-locked loop circuit, a control signal based on a first clock signal and a first divider value;
• generating, by a voltage-controlled oscillator, an output clock signal based on the control signal;
• calculating, by a target frequency calculation circuit, a target frequency ratio of a second phase-locked loop circuit based on a frequency offset ratio of the first clock signal with respect to a reference signal measured at a first time interval and a frequency offset ratio of a second clock signal with respect to the reference signal measured at a second time interval after the first phase-locked loop circuit is closed;
• calculating, by the target frequency calculation circuit, a target frequency based on the target frequency ratio, the target frequency independent from the output clock signal generated by the voltage-controlled oscillator;
• and
• generating, by the second phase-locked loop circuit, an adjusted first divider value for the first phase-locked loop circuit according to the target frequency based on the second clock signal and a second divider value.