Adding LUT fracturabiliy to FPGA 4-LUTs using existing adder circuitry
AssigneeEfinix, Inc.
InventorMarcel Gort
Life of this patent
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Abstract
A field programmable gate array (FPGA) has a 4-LUT (lookup table) that has four stages of multiplexers. The 4-LUT is fracturable. The 4-LUT being fracturable includes the capability to implement multiple LUTs in an instance of FPGA programming for functions from a group that includes adder functions and further functions. The 4-LUT has outputs exposed to programmable connection in accordance with FPGA programming. Outputs of the 4-LUT include an output of a first multiplexer in the third stage, an output of a multiplexer in the second stage, and an output of a multiplexer in the second or third stage of the 4-LUT.
Claims20
A field programmable gate array (FPGA), comprising:
- a 4-LUT (lookup table) comprising first, second, third and fourth stages of multiplexers;
- the 4-LUT being fracturable to implement a plurality of LUTs in an instance of FPGA programming for functions from a group comprising adder functions and further functions;
- and
- the 4-LUT having outputs exposed to programmable connection in accordance with the FPGA programming, including an output of a first multiplexer in the third stage, an output of a first multiplexer in the second stage, and an output of a multiplexer in the second or third stage.
A method of operation of a field programmable gate array (FPGA), comprising:
- fracturing a 4-LUT having first, second, third and fourth stages of multiplexers, to implement a plurality of LUTs each having fewer than four stages of multiplexers for functions from a group comprising adder functions and further functions;
- and
- programming connection of at least two of a plurality of outputs of the 4-LUT to further implement the plurality of LUTs from the 4-LUT in an instance of FPGA programming, wherein the plurality of outputs of the 4-LUT comprises an output of a first multiplexer in a third stage of the 4-LUT, an output of a first multiplexer in a second stage of the 4-LUT, and an output of a multiplexer in the second or third stage of the 4-LUT.
A tangible, non-transitory, computer-readable media having instructions thereupon which, when executed by a processor, cause the processor to perform a method comprising:
- fracturing a 4-LUT having first, second, third and fourth stages of multiplexers, to implement a plurality of LUTs each having fewer than four stages of multiplexers, for functions from a group comprising adder functions and further functions, the 4-LUT being fracturable and in a field programmable gate array (FPGA);
- and
- programming connection of at least two of a plurality of outputs of the 4-LUT to further implement the plurality of LUTs from the 4-LUT in an instance of FPGA programming, wherein the plurality of outputs of the 4-LUT comprises an output of a first multiplexer in a third stage of the 4-LUT, an output of a first multiplexer in a second stage of the 4-LUT, and an output of a multiplexer in the second or third stage of the 4-LUT.
Dependencies are inferred from the claim text.