Clock signal receiver circuit with active inductance, common mode voltage source, and negative capacitance

An apparatus, comprising:

• a common mode voltage generator configured to generate a common mode voltage at an output, wherein the common mode voltage generator comprises:
• a current source configured to generate a first current;
• one or more current mirrors configured to generate a second current based on the first current;
• and
• one or more diode-connected FETs configured to generate the common mode voltage based on the second current;
• an input circuit comprising:
• a first field effect transistor (FET);
• a second FET;
• a first capacitor coupled between a first differential clock input and a first gate of the first FET;
• a second capacitor coupled between a second differential clock input and a second gate of the second FET;
• a first resistive device coupled between the output of the common mode voltage generator and the first gate of the first FET;
• and
• a second resistive device coupled between the output of the common mode voltage generator and the second gate of the second FET;
• and
• an active inductance circuit coupled in series with the input circuit between an upper voltage rail and a lower voltage rail, respectively.