Memory device including repair circuit and operating method thereof

A memory device comprising:

• a merged bank comprising memory cells coupled to a plurality of word lines;
• a row decoder configured to transmit a row select signal through the plurality of word lines and to select at least one word line of the merged bank;
• and
• a repair circuit configured to repair a fail address corresponding to the selected word line,
• wherein the merged bank comprises a first bank and a second bank, and
• wherein the repair circuit comprises:
• a first fail address latch configured to latch a first fail address and a second fail address corresponding to the first bank;
• a second fail address latch configured to latch a third fail address and a fourth fail address corresponding to the second bank;
• a fail address multiplexer configured to output a first merge address by merging the first fail address with the third fail address, and to output a second merge address by merging the second fail address with the fourth fail address;
• a comparison circuit configured to compare a logic level of the first merge address with logic levels of merged decoded row addresses to generate a first hit signal, and to compare a logic level of the second merge address with logic levels of the merged decoded row addresses to generate a second hit signal;
• a logic operator configured to receive the first hit signal and the second hit signal, and to output a valid hit pre-signal;
• and
• a valid hit latch configured to receive the valid hit pre-signal and to output a valid hit signal.

An operating method of a memory device including a repair circuit for repairing addresses of two or more merged banks, the operating method comprising:

• receiving a first fail address pre-signal of a first bank and obtaining a first fail address;
• receiving a second fail address pre-signal of a second bank and obtaining a second fail address;
• receiving a third fail address pre-signal of a third bank and obtaining a third fail address;
• receiving a third fail address pre-signal of a fourth bank and obtaining a fourth fail address;
• generating a first merge address based on the first fail address and the second fail address;
• generating a second merge address based on the third fail address and the fourth fail address;
• generating a first hit signal by comparing a logic level of a first merged decoded row address with a logic level of the first merge address;
• generating a second hit signal by comparing a logic level of a second merged decoded row address with a logic level of the second merge address;
• generating a valid hit pre-signal based on the first hit signal and the second hit signal;
• and
• outputting a valid hit signal based on the valid hit pre-signal.