Systems and methods for testing error correction code (ECC) logic of automotive safety systems for faults

A method for testing error correction coding (ECC) logic of at least a first memory device, the ECC logic being used to check memory of at least a first memory device for bit errors, the method comprising:

• using fault injection logic to cause a first preselected test bit pattern to be injected into the ECC logic and sent to ECC syndrome generator logic of the ECC logic, the ECC syndrome generator logic processing the injected first preselected test bit pattern to generate a first ECC syndrome that is stored in a first ECC memory of the first memory device;
• using the fault injection logic to retrieve the first ECC syndrome from the first ECC memory, alter the first ECC syndrome by inverting one or more bits and send the altered first ECC syndrome to the ECC checker logic, the ECC checker logic receiving the altered first ECC syndrome and processing the altered first ECC syndrome to generate a first fault signature that is logged by an ECC logger;
• and
• using fault decision logic to compare the logged first fault signature with an expected fault signature to determine whether the logged first fault signature matches the expected fault signature.

A computer program for testing error correction coding (ECC) logic of at least a first memory device, the ECC logic being used to check memory of at least the first memory device for bit errors, the computer program comprising computer instructions for execution by a processor, the computer program being embodied on a non-transitory computer readable medium, the computer program comprising:

• a first set of computer instructions for causing fault injection logic to inject a first preselected test bit pattern into the ECC logic;
• a second set of computer instructions for causing the fault injection logic to send the first preselected test bit pattern to ECC syndrome generator logic of the ECC logic, the ECC syndrome generator logic processing the first preselected test bit pattern to generate a first ECC syndrome that is stored in a first ECC memory of the first memory device;
• a third set of computer instructions for causing the fault injection logic to retrieve the first ECC syndrome from the first ECC memory, alter the first ECC syndrome by inverting one or more bits and send the altered first ECC syndrome to ECC checker logic of the ECC logic for processing of the altered first ECC syndrome to generate a first fault signature that is logged by an ECC logger;
• and
• a fourth set of computer instructions for causing fault decision logic to compare the logged first fault signature with an expected fault signature to determine whether the logged first fault signature matches the expected fault signature.

An error correction coding (ECC) test system for testing ECC logic of at least a first memory device, the ECC logic being used to check memory of at least the first memory device for bit errors, the ECC logic comprising ECC syndrome generator logic and ECC checker logic, the ECC test system comprising:

• means for injecting a preselected test bit pattern into the ECC logic for processing by the ECC syndrome generator logic to generate an ECC syndrome that is stored in a first ECC memory of the first memory device;
• means for retrieving the ECC syndrome from the first ECC memory;
• means for altering the retrieved ECC syndrome by inverting one or more bits;
• means for causing the altered ECC syndrome to be sent to the ECC checker logic for processing by the ECC checker logic to generate a fault signature that is logged by an ECC logger;
• and
• means for receiving the logged fault signature from the ECC logger and for comparing the logged fault signature with an expected fault signature to determine whether the logged fault signature matches the expected fault signature.