Pseudo multi-port memory with memory cells each having two-port memory cell architecture and multiple enable pulses on same wordline and associated memory access method

A pseudo multi-port memory comprising:

• a memory array, comprising:
• a plurality of read wordlines (RWLs);
• a plurality of write wordlines (WWLs);
• and
• a plurality of memory cells, wherein each of the plurality of memory cells is coupled to one of the plurality of RWLs and one of the plurality of WWLs, and has a two-port memory cell architecture;
• a row decoder circuit, arranged to generate and output an RWL signal to a selected RWL, and generate and output a WWL signal to a selected WWL, wherein a selected memory cell of the plurality of memory cells is coupled to the selected RWL and the selected WWL;
• a timing controller circuit, arranged to generate and output a timing control signal to the row decoder circuit, wherein during one memory clock cycle of the pseudo multi-port memory, the row decoder circuit is controlled by the timing control signal to make the RWL signal have an enable pulse and the WWL signal have a plurality of enable pulses;
• a sense amplifier circuit, arranged to perform a read operation upon the selected memory cell when the selected RWL is enabled by the enable pulse, and is further arranged to perform at least one read operation upon the selected memory cell when the selected WWL is enabled by at least one first enable pulse included in the plurality of enable pulses;
• and
• a write driver circuit, arranged to perform a write operation upon the selected memory cell when the selected WWL is enabled by one second enable pulse included in the plurality of enable pulses.