Computer architecture using program counter indexed data address translation
AssigneeWisconsin Alumni Research Foundation
InventorsGurindar Sohi, Shyam Murthy
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Abstract
Translation between virtual memory addresses and physical memory addresses is mediated by a program counter indexed table holding virtual and corresponding physical addresses. In some embodiments, this table can be accessed early in the fetch cycle and avoid likely TLB misses.
Claims20
An architecture of a computer processor providing a program counter (PC) for fetching instructions from a memory system, the memory system holding a given instruction identified by a given program counter (PC) value, the given instruction accessing data at a target virtual memory address;
- the memory system further holding a page table, an entry in the page table identifying a corresponding physical memory address for a given virtual memory address;
- the architecture comprising:
- a program counter indexed address translation table (PCAT) having rows accessed with a program counter (PC) value, an entry in a row identifying a virtual memory address and a corresponding physical memory address;
- translation circuitry operating to access the PCAT with the given program counter (PC) value of a given instruction to obtain the physical memory address corresponding to the target virtual memory address of the data the given instruction is accessing.
A method of operating a computer architecture having a computer processor providing a program counter (PC) for fetching instructions from a memory system, the memory system holding a given instruction identified by a given program counter (PC) value, the given instruction accessing data at a target virtual memory address;
- the memory system further holding a page table, an entry in the page table identifying a corresponding physical memory address for a given virtual memory address;
- the architecture further including a program counter indexed address translation table (PCAT) having rows accessed with a program counter (PC) value, an entry in a row identifying a virtual memory address and a corresponding physical memory address;
- the method comprising:
- receiving a given instruction associated with a given program counter (PC) value;
- obtaining a physical memory address corresponding to a target virtual memory address of the data the given instruction is accessing by accessing the PCAT with the given program counter (PC) value of a given instruction.
Dependencies are inferred from the claim text.