Computing system and method for power-saving compute-in-memory design

A computing system with a compute-in-memory (CIM) design, comprising:

• a CIM processor, including a processor control unit, a CIM memory with CIM capability, and a register file;
• and
• a two-level memory system coupled to the CIM processor, wherein the two-level memory system includes a first-level (L1) memory and a second-level (L2) memory;
• wherein:
• the processor control unit loads A blocks divided from a matrix AM×K from the L2 memory to the L1 memory, and loads B blocks divided from a matrix BK×N from the L2 memory to the CIM memory;
• the processor control unit further programs the A blocks buffered in the L1 memory to the register file to be entered into the CIM memory, wherein the CIM memory performs multiply-and-accumulate (MAC) calculations on the A blocks and the B blocks to generate C blocks which form a matrix CM×N that is AM×K×BK×N;
• and
• based on size of the matrix AM×K, size of the matrix BK×N, an A block buffering capability, μ, of the L1 memory, and a B block buffering capability, L, of the CIM memory, the CIM processor selects a reuse scheme to reuse the A blocks buffered in the L1 memory and the B blocks buffered in the CIM memory.