Interleave circuit and communication device
AssigneeKabushiki Kaisha Toshiba
InventorsYutaro Ishigaki, Kazuaki Doi
Life of this patent
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Abstract
According to an embodiment, an interleave circuit includes a reordering circuit and an address calculation circuit. The reordering circuit is configured to, for each cycle, receive in parallel input data containing n (n is an integer of 2 or more) bits, and reorder n-pieces of the input data input in n cycles into n-pieces of output data each containing n bits input in cycles different from each other. The address calculation circuit is configured to calculate write addresses for writing the n-pieces of output data into a first storage device and read addresses for reading out the n-pieces of output data from the first storage device.
Claims6
An interleave circuit comprising:
- a reordering circuit configured to:
- for each cycle, receive in parallel n (n is an integer of 2 or more) bits contained in a piece of input data;
- and
- after receiving n-pieces of input data in n cycles, reorder the n-pieces of input data into n-pieces of output data, each piece of output data containing n bits received in cycles different from each other;
- and
- an address calculation circuit configured to calculate addresses for a first storage device for storing the n-pieces of output data,
- wherein
- the reordering circuit includes, for each of the ith (0≤i≤n−1) bit positions of the input data, registers of (n+i) stages, each functioning as a shift register,
- the reordering circuit includes n selection circuits,
- a jth (0≤j≤n−1) selection circuit among the n selection circuits:
- is connected to registers of (n−j+i) stages among the registers of (n+i) stages corresponding to the ith (0≤i≤n−1) bit positions of the input data;
- and is configured to, in each of consecutive n cycles, select bits stored in registers different from each other among the connected registers, and
- the reordering circuit outputs the output data containing n bits selected by the n selection circuits.
A communication device comprising:
- an interleave circuit outputting output data that is reordered from input data;
- and
- a processor configured to execute error correction on the output data,
- the interleave circuit comprising:
- a reordering circuit configured to:
- for each cycle, receive in parallel n (n is an integer of 2 or more) bits contained in a piece of input data;
- and
- after receiving n-pieces of input data in n cycles, reorder the n-pieces of input data into n-pieces of output data, each piece of output data containing n bits received in cycles different from each other;
- and
- an address calculation circuit configured to calculate addresses for a first storage device for storing the n-pieces of output data,
- wherein
- the reordering circuit includes, for each of the ith (0≤i≤n−1) bit positions of the input data, registers of (n+i) stages, each functioning as a shift register,
- the reordering circuit includes n selection circuits,
- a jth (0≤j≤n−1) selection circuit among the n selection circuits:
- is connected to registers of (n−j+i) stages among the registers of (n+i) stages corresponding to the ith (0≤i≤n−1) bit positions of the input data;
- and is configured to, in each of consecutive n cycles, select bits stored in registers different from each other among the connected registers, and
- the reordering circuit outputs the output data containing n bits selected by the n selection circuits.
Dependencies are inferred from the claim text.