Techniques for memory error isolation
AssigneeNVIDIA Corporation
InventorsJonathon Stuart Ramsay Evans, Naveen Cherukuri, Jerome Francis Duluk, Jr., Shailendra Singh, Vaibhav Vyas, Wishwesh Gandhi, Arvind Gopalakrishnan, Manas Mandal
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Abstract
Apparatuses, systems, and techniques to detect memory errors and isolate or migrate partitions on a parallel processing unit using an application programming interface to facilitate parallel computing, such as CUDA. In at least one embodiment, interrupts are intercepted and processed on a graphics processing unit indicating a memory error for one or more partitions, and a policy is applied to isolate that memory error from other partitions.
Claims40
One or more processors, comprising:
- circuitry to:
- cause one or more graphics processing unit (GPU) slices to be associated with a second one or more storage locations based, at least in part, on whether an error is detected within a first one or more storage locations;
- and
- facilitate migration of the one or more GPU slices based, at least in part, on whether the error is detected within the first one or more storage locations.
A system comprising:
- one or more processors to cause one or more graphics processing unit (GPU) slices to be associated with a second one or more storage locations based, at least in part, on whether an error is detected within a first one or more storage locations;
- and
- facilitate migration of the one or more GPU slices based, at least in part, on whether the error is detected within the first one or more storage locations.
A non-transitory machine-readable medium having stored thereon instructions which, if performed by one or more processors, cause the one or more processors to at least:
- cause one or more graphics processing unit (GPU) slices to be associated with a second one or more storage locations based, at least in part, on whether an error is detected within a first one or more storage locations;
- and
- facilitate migration of the one or more GPU slices based, at least in part, on whether the error is detected within the first one or more storage locations.
A method comprising:
- causing one or more graphics processing unit (GPU) slices on one or more parallel processing units to be associated with a second one or more storage locations based, at least in part, on whether an error is detected within a first one or more storage locations;
- and
- facilitate migration of the one or more GPU slices based, at least in part, on whether the error is detected within the first one or more storage locations.
Dependencies are inferred from the claim text.