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US 12,517,652 B2Granted
Memory management
AssigneeMicron Technology, Inc.
InventorsHoria C. Simionescu, Chung Kuang Chin
Life of this patent
Estimating the term…
Abstract
Managed units (MUs) of data can be stored on a memory device according to a slice-based layout. A slice of the slice-based layout can include a plurality of stripes, each of the stripes including respective partitions and respective MUs of data. A subset of the stripes each include a quantity of partitions and a first quantity of MUs of data. Another subset of the stripes each include a lesser quantity of partitions and a lesser quantity of MUs of data.
Claims18
A method, comprising:
- writing managed units (MUs) of data to a memory device according to a stripe-based layout, wherein:
- each stripe of the stripe-based layout comprises a respective plurality of partitions of the memory device,
- each partition of the memory device corresponds to more than one stripe, and
- each MU of data is associated with a respective stripe;
- and
- translating an address of a target MU of data to a particular stripe address, wherein translating a target MU address comprises dividing the target MU address by a quantity of channels of the memory associated with the MUs of data to obtain the particular stripe address.
3 more elements
An apparatus, comprising:
- a memory device of a memory system;
- and
- a management component configured to:
- store managed units (MUs) of data and parity MUs on the memory device according to a stripe-based layout such that each stripe of the stripe-based layout comprises a plurality of partitions of the memory device, wherein:
- each partition of the memory device corresponds to more than one stripe, and
- each MU of data is associated with a respective stripe;
- and
- cause execution of commands associated with each respective stripe according to a plurality of scheduling policies, wherein the management component further comprises a respective plurality of first in first outs (FIFOs) for each channel of the memory device, wherein a quantity of FIFOs for each channel of the memory device is equal to a quantity of stripes for each respective memory address.
5 more elements
A non-transitory medium storing instructions executable by a processing device to:
- determine whether a stripe address corresponding to a managed unit (MU) address of a command associated with a memory device is stored in a plurality of hash tables of a controller coupled to the memory device;
- and
- in response to determining the stripe address is stored in the plurality of hash tables, retrieve the command from a buffer of the controller.
Dependencies are inferred from the claim text.