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US 12,517,548 B2Granted
Synchronised multi-processor operating system timer
AssigneeNordic Semiconductor ASA
InventorFrode Milch Pedersen
Life of this patent
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Abstract
An integrated-circuit device comprises a plurality of processor cores and a system timer. The system timer includes a first oscillator that outputs a first clock signal at a first frequency, a first counter register incremented by the first clock signal and a plurality of event registers. Each event register triggers an event when a value held therein is determined to be equal to a value held in the first counter register. The first counter register is readable by each of the plurality of processor cores, and each of the processor cores are capable of writing to at least one of the event registers.
Claims19
An integrated-circuit device comprising:
- a plurality of processor cores;
- a computer readable storage medium comprising instructions for execution by one or more of the processor cores, each of the instructions being associated with a respective one of a plurality of security settings;
- and
- a system timer comprising:
- a first oscillator configured to output a first clock signal at a first frequency;
- a first counter register incremented by the first clock signal;
- and
- a plurality of event registers, each event register being configured to trigger an event when a value held therein is determined to be equal to a value held in the first counter register;
- wherein
- the first counter register is configured to be readable by each of the plurality of processor cores;
- each of the processor cores are configured to be capable of writing to at least one of the event registers;
- each of the plurality of processor cores is associated with a respective one of a plurality of owner IDs;
- and
- at least one event register is associated with a respective one of the plurality of owner IDs and a respective one of the plurality of security settings, wherein said event register is configured to be writeable to only by a processor core that is associated with said respective owner ID and executing instructions associated with said respective security setting.
11 more elements
An integrated-circuit device comprising:
- a plurality of processor cores;
- and
- a system timer comprising:
- a first oscillator configured to output a first clock signal at a first frequency;
- a first counter register incremented by the first clock signal;
- a plurality of event registers, each event register being configured to trigger an event when a value held therein is determined to be equal to a value held in the first counter register;
- and
- a count offset register for storing a configurable count offset value and configured to be writeable to by at least one of the processor cores
- wherein
- the first counter register is configured to be readable by each of the plurality of processor cores;
- each of the processor cores are configured to be capable of writing to at least one of the event registers;
- and
- wherein each of the processor cores are configured to write to an event register by writing a count offset value to the count offset register and transmitting a signal indicating the event register to be written to.
10 more elements
An integrated-circuit device comprising:
- a plurality of processor cores;
- and
- a system timer comprising:
- a first oscillator configured to output a first clock signal at a first frequency;
- a first counter register incremented by the first clock signal;
- a plurality of event registers, each event register being configured to trigger an event when a value held therein is determined to be equal to a value held in the first counter register;
- a high-resolution timer comprising the first oscillator and the first counter register;
- and
- a low-resolution timer comprising a second oscillator configured to output a second clock signal at a second frequency and a second counter register incremented by the second clock signal, the second frequency being less than the first frequency;
- wherein
- the first counter register is configured to be readable by each of the plurality of processor cores;
- each of the processor cores are configured to be capable of writing to at least one of the event registers;
- the device is configured to operate in one of a plurality of states, the plurality of states comprising:
- an active state in which both the high-resolution timer and the low-resolution timer are enabled;
- and
- a sleep state in which the high-resolution timer is disabled and the low-resolution timer is enabled;
- and
- the device is configured to transition from the sleep state to the active state, said transition comprising writing a value to the first counter register based on a value held in the second counter register.
15 more elements
Dependencies are inferred from the claim text.