Clock adjustment circuit using pattern filter circuit to select predetermined data patterns for phase error detection under acquisition mode and tracking mode and associated clock adjustment method

A clock adjustment circuit comprising:

• a pattern filter circuit, arranged to select first predetermined data patterns from a plurality of consecutive data samples under an acquisition mode of the clock adjustment circuit, wherein the plurality of consecutive data samples are derived from an output of a first sampler circuit;
• a phase error detector (PED) circuit, arranged to detect phase errors according to an output of the pattern filter circuit and error samples derived from an output of a second sampler circuit;
• a phase error calculation circuit, arranged to determine timing compensation of a sampling clock according to an output of the PED circuit, wherein the sampling clock is used by the first sampler circuit and the second sampler circuit;
• and
• a pattern switch control circuit, wherein in response to the clock adjustment circuit being switched from the acquisition mode to a tracking mode, the pattern switch control circuit is arranged to instruct the pattern filter circuit to select second predetermined data patterns from the plurality of consecutive data samples under the tracking mode of the clock adjustment circuit;
• and each of the second predetermined data patterns is different from any of the first predetermined data patterns.