US 12,517,544 B2Granted

Power reduction and effective timing exceptions handling in at-speed capture

AssigneeSTMicroelectronics International N.V.

InventorsVenkata Narayanan Srinivasan, Shiv Kumar Vats, Umesh Chandra Srivastava

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Abstract

According to an embodiment, a method for testing a scan chain is provided. The method includes receiving a first clock signal and a first scan enable signal and generating a second and third clock signal based on the first clock signal and the first scan enable signal. The third clock signal is delayed by a clock pulse from the second clock signal. The first, second, and third clock signal have the same duty cycle. The method further includes providing the second clock signal and the second scan enable signal to, respectively, a clock terminal and scan enable input of a first scan flip-flop of the scan chain. The method further includes providing the third clock signal and a third scan enable signal to, respectively, a clock terminal and a scan enable input of a last scan flip-flop of the scan chain.

A control circuit, comprising:

a first flip-flop, a data terminal of the first flip-flop configured to receive a first scan enable signal, a clock terminal of the first flip-flop configured to receive a first clock signal, an output terminal of the first flip-flop configured to provide a first latched scan enable signal;
a first NOT gate configured to receive the first latched scan enable signal and provide an inverted first latched scan enable signal;
a first multiplexer, a first input of the first multiplexer configured to receive a first test control signal, a second input of the first multiplexer configured to receive a second test control signal, a third input of the first multiplexer configured to receive the first latched scan enable signal, a fourth input of the first multiplexer configured to receive the inverted first latched scan enable signal, a first select terminal of the first multiplexer configured to receive a first select signal, and a second select terminal of the first multiplexer configured to receive a second select signal;
a second multiplexer, a first input of the second multiplexer configured to receive a functional logic signal, a second input of the second multiplexer configured to receive an output signal from the first multiplexer in accordance with the first select signal and the second select signal, and a select terminal of the second multiplexer configured to receive a third test control signal;
a first OR gate, a first input of the first OR gate configured to receive the first scan enable signal, a second input of the first OR gate configured to receive a fourth test control signal;
a second OR gate, a first input of the second OR gate coupled to an output of the first OR gate, a second input of the second OR gate configured to receive an output signal from the second multiplexer in accordance with the third test control signal;
and
a first clock gate circuit comprising a first latch coupled to a first AND gate, a data terminal of the first latch coupled to an output of the second OR gate, a gated negative-set terminal of the first latch configured to receive the first clock signal, the first clock gate circuit configured to provide a second clock signal.

5 more elements

Facts

Application

18/337,720Filed 20 Jun 2023

Published

US 2024/0427366 A126 Dec 2024

Granted

6 Jan 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

G01R 31/318541
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: scan latches or cell details
G06F 1/06
Generating or distributing clock signals or signals derived directly therefrom: clock generators producing several clock signals
G01R 31/318552
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: clock circuits details
G01R 31/318575
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: power distribution; Power saving

Abstract

Claims20