Methods of fabricating porous silicon structures
AssigneeThe Methodist Hospital
InventorXuewu Liu
Life of this patent
Estimating the term…
Abstract
The present disclosure provides methods of manufacturing porous silicon structures having controlled sizes, shapes, and porosity by using a series of protective layers and selective etching steps. A benefit of the methods disclosed herein can be providing microfabrication and nanofabrication methods that are capable of provide porous silicon structures having sizes, shapes, and porosity that are more tightly controlled by avoiding inadvertently etching parts of the silicon structures during the fabrication process.
Claims18
A method of manufacturing porous silicon structures comprising:
- providing a silicon substrate having a silicon surface, wherein the silicon substrate is a heavily doped p++ type wafer with resistivity ranging from about 0.003 ohm-cm to about 0.007 ohm-cm;
- forming a first protective layer on the silicon surface, wherein the first protective layer has a protective layer surface, wherein the first protective layer comprises silicon oxide;
- depositing a second protective layer on the protective layer surface;
- forming protected areas and non-protected areas on the first protective layer surface by patterning the second protective layer;
- forming first protective layer pillars by performing a first etch of the non-protected areas of the first protective layer;
- forming silicon pillars by performing a second etch of the silicon substrate, wherein the silicon pillars are located beneath the first protective layer pillars, wherein the silicon pillars have a silicon pillar top, a silicon pillar sidewall, a silicon pillar height, and a silicon pillar width, and wherein adjacent silicon pillar sidewalls are separated by silicon trenches having a silicon pillar spacing,
- covering the first protective layer pillars, the silicon pillar sidewalls, and the silicon trenches by depositing a dielectric layer;
- patterning the dielectric layer by removing a portion of the dielectric layer from a top of the protective layer pillars by exposing the dielectric layer to a third etch;
- and
- removing the protective layer pillars by exposing the protective layer pillars to a fourth etch.
A method of manufacturing porous silicon structures comprising:
- providing a silicon substrate having a silicon surface, wherein the silicon substrate is a heavily doped p++ type wafer with resistivity ranging from about 0.003 ohm-cm to about 0.007 ohm-cm;
- forming a first protective layer on the silicon surface, wherein the first protective layer has a protective layer surface, wherein the first protective layer comprises silicon oxide;
- depositing a second protective layer on the protective layer surface;
- forming protected areas and non-protected areas on the first protective layer surface by patterning the second protective layer;
- forming first protective layer pillars by performing a first etch of the non-protected areas of the first protective layer;
- forming silicon pillars by performing a second etch of the silicon substrate, wherein the silicon pillars are located beneath the first protective layer pillars, wherein the silicon pillars have a silicon pillar top, a silicon pillar sidewall, a silicon pillar height, and a silicon pillar width, and wherein adjacent silicon pillar sidewalls are separated by silicon trenches having a silicon pillar spacing,
- covering the first protective layer pillars, the silicon pillar sidewalls, and the silicon trenches by depositing a dielectric layer;
- patterning the dielectric layer by removing a portion of the dielectric layer from a top of the protective layer pillars by exposing the dielectric layer to a third etch;
- and
- removing the first protective layer pillars by exposing the protective layer pillars to a fourth etch;
- wherein the third etch comprises reactive ion etching under an atmosphere of CF4, CHF3, or SF6;
- and
- wherein a ratio of the silicon pillar height to silicon pillar spacing is from about 60:1 to about 20:1.
Dependencies are inferred from the claim text.