US 12,513,978 B2Granted

Manufacturing method for a power semiconductor device and power semiconductor device

AssigneeHitachi Energy Ltd

InventorsStephan Wirths, Lars Knoll

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Abstract

The present disclosure relates to a manufacturing method for a power semiconductor device (1, 40), comprising: forming multiple growth templates on a carrier substrate (2), comprising at least a first plurality of hollow growth templates (18) and a second plurality of hollow growth templates (28); selectively growing a first sequence of differently doped wide bandgap semiconductor materials in each one of the first hollow growth templates (18), thereby forming a corresponding plurality of first semiconductor structures (5) of a first type, in particular n+/p−/n−/n+ structures; and selectively growing a second sequence of differently doped wide bandgap semiconductor materials in each one of the second hollow growth templates (28), thereby forming a corresponding plurality of second semiconductor structures (6) of a second type, in particular n+/n−/p−/n+ structures. The disclosure further relates to a power semiconductor device (1, 40) comprising a carrier substrate (2), at least one dielectric layer (4, 27, 31), a plurality of first semiconductor structures (5) of a first type, and a plurality of second semiconductor structures (6) of a second type formed within the at least one dielectric layer (4, 27, 31).

Claims14

Dependent claims

A manufacturing method for a power semiconductor device, comprising:

forming multiple growth templates on a carrier substrate, comprising at least a first plurality of hollow growth templates and a second plurality of hollow growth templates;
selectively growing a first sequence of differently doped wide bandgap, WBG, semiconductor material in each one of the first hollow growth templates, thereby forming a corresponding plurality of first semiconductor structures of a first type;
forming a plurality of first gate structures, each one of the first gate structures surrounding at least a channel area of a corresponding one of the plurality of first semiconductor structures;
forming at least one dielectric layer, wherein the first gate structures are buried in the at least one dielectric layer;
selectively growing a second sequence of differently doped WBG semiconductor material in each one of the second hollow growth templates, wherein the second sequence differs from the first sequence, thereby forming a corresponding plurality of second semiconductor structures of a different, second type;
and
forming a plurality of second gate structures, each one of the second gate structures surrounding at least a channel area of a corresponding one of the plurality of second semiconductor structures, wherein the second gate structures are formed at closer to an upper surface of the at least one dielectric layer than the first gate structures, such that the first gate structures and the second gate structures vertically offset with respect to each other, wherein the plurality of first semiconductor structures are connected in parallel to allow for an increase in current density, and wherein the plurality of first semiconductor structures of the first type and the plurality of second semiconductor structures of the second type are connected in sequence to form a half-bridge.

4 more elements

A power semiconductor device, comprising:

a carrier substrate comprising at least one bottom contact;
at least one dielectric layer formed on the carrier substrate;
a plurality of first semiconductor structures of a first type formed within the at least one dielectric layer, each one of the first semiconductor structures electrically connected to the bottom contact and comprising a first sequence of differently doped sublayers of a wide bandgap, WBG, semiconductor material;
a plurality of buried first gate structures arranged within the at least one dielectric layer, each one of the first gate structures surrounding a channel area of a corresponding one of the first semiconductor structures;
a plurality of second semiconductor structures of a different, second type formed within the at least one dielectric layer, each one of the second semiconductor structures electrically connected to the bottom contact and comprising a second sequence of differently doped sublayers of the WBG semiconductor material, wherein the second sequence differs from the first sequence;
a plurality of second gate structures arranged at closer to an upper surface of the at least one dielectric layer than the first gate structures, each one of the second gate structures surrounding a channel area of a corresponding one of the second semiconductor structures, wherein the first gate structures and the second gate structures are vertically offset with respect to each other,
a first top side contact arranged on the upper surface of the at least one dielectric layer, the first top side contact electrically connecting at least a subgroup of the plurality of first semiconductor structures;
and
a second top side contact arranged on the upper surface of the at least one dielectric layer, the second top side contact electrically connecting at least a subgroup of the plurality of second semiconductor structures, wherein the first semiconductor structures of the first type are n+/p−/n−/n+ semiconductor structures from bottom to top starting from the carrier substrate, and the second semiconductor structures of the second type are n+/n−/p−/n+ semiconductor structures from bottom to top starting from the carrier substrate.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/119,588Filed 10 Oct 2022
Published: US 2025/0261443 A114 Aug 2025
Granted: 30 Dec 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification21 codes

H10D 62/151
Source or drain regions of field-effect devices: of igfets
H10D 84/8311
Of only insulated-gate FETs [IGFET]: the IGFETs characterised by having different channel structures
H02M 7/5387
Using semiconductor devices only, e.g. single switched pulse inverters: in a bridge configuration
H10D 30/019
Manufacture or treatment: of FETs having stacked nanowire, nanosheet or nanoribbon channels