Semiconductor device with self-aligned channel and self-aligned contact region, and method of preparing the same

A method to make a semiconductor device having a source region self-aligned with a body region and a body contact region self-aligned with the body region, comprising

• 1) providing a semiconductor substrate;
• 2) depositing a semiconductor buffer layer of a first conductivity doping type on the semiconductor substrate;
• 3) depositing one or more semiconductor epitaxial layers of the first conductivity doping type on the buffer layer and forming a drift layer;
• 4) forming through depositing or growing a thin layer (M0) on a topmost epitaxial layer, wherein the said thin layer (M0) is configured to adjust profiles of implanted ions and to protect the topmost epitaxial layer;
• 5) depositing and patterning a first hard mask material to produce a first hard mask (M1), wherein the first hard mask has a thickness to block the implanted ions;
• 6) forming a body region of a second conductivity doping type by ion implantation, using the first hard mask (M1) as a mask;
• and forming Junction Field-Effect Transistor (JFET) regions between the body regions of neighboring cells;
• 7) depositing a second hard mask material on top of the first hard mask (M1) and the thin layer (M0);
• 8) etching the second hard mask material to create a second hard mask (M2) as a spacer mask on sidewalls of the first hard mask (M1), a width of the spacer mask equals a thickness of the deposited second hard mask material;
• 9) forming a source region of the first conductivity doping type by ion implantation, using the first hard mask (M1) and the second hard mask (M2), making the source region self-aligned with the body region, creating a channel between the JFET region and the source region at a shallow depth in the body region;
• 10) forming a body contact region of the second conductivity doping type by ion implantation, wherein the body contact region and the source region are vertically aligned, each being laterally positioned in accordance with inner edges of the second hard mask (M2);
• wherein the channel between the JFET region and the source region in the body region is vertically aligned with second hard mask (M2), said vertical alignments are achieved essentially through the use of the first hard mask (M1) and the second hard mask (M2);
• 11) removing the thin layer (M0), the first hard mask (M1) and the second hard mask (M2) by wet etching or dry etching with high selectivity to the semiconductor material;
• 12) activating the implanted ions, forming a gate insulator, forming a gate and forming an interlayer dielectric enclosing the gate;
• 13) etching an ohmic contact via in the interlayer dielectric using a contact mask and using the same contact mask to etch a trench in the source region to access the body contact region;
• 14) removing the contact mask and depositing an ohmic metal layer on top and sidewalls of the interlayer dielectric and on bottom and sidewalls of the semiconductor trenches;
• 15) annealing the ohmic metal using a first contact annealing process to form a self-aligned metal and semiconductor alloy on the trench bottom and sidewalls;
• 16) removing the unalloyed ohmic metal from the interlayer dielectric and semiconductor, leaving the metal and semiconductor alloy intact, and annealing the metal and semiconductor alloy using a second contact annealing process to achieve final properties of ohmic contacts;
• source contact defined by an overlap of the alloy with the source region on the sidewalls of the semiconductor trenches, body contact defined by an overlap of the alloy with the body contact region on the bottom of the semiconductor trenches;
• 17) processing the semiconductor device, including etching a gate contact via, depositing and patterning front side metallization, depositing and patterning passivation, and forming backside metallization.