Vertical-structure field-effect transistor and manufacturing method therefor

A vertical-structure field-effect transistor comprising:

• a gate electrode formed on a substrate and having a horizontal plane extending in a plane direction and a vertical plane extending in a height direction;
• a gate insulating layer covering the gate electrode;
• a vertical channel formed on the gate insulating layer, in which a channel is formed in the height direction;
• a source electrode coming into contact with one end of the vertical channel;
• and
• a drain electrode coming into contact with an opposite end of the vertical channel, and formed at a height level different from a height level of the source electrode, wherein
• a channel on-off state of the vertical channel is controlled by an electric field formed to the vertical channel in the vertical plane of the gate electrode, and
• at least one of the source electrode and the drain electrode does not overlap (non-overlaps) the gate electrode in the height direction of the gate electrode,
• wherein the vertical channel has a vertical portion extending in the height direction and a horizontal portion extending in the plane direction, and the vertical portion overlaps the gate electrode in the plane direction while not overlapping the gate electrode in the height direction,
• wherein the horizontal portion includes an upper horizontal portion extending in the plane direction from the upper end of the vertical portion toward the gate electrode, and the upper horizontal portion is layered in the height direction with one of the source electrode and the drain electrode, and partially overlaps in the height direction with the gate electrode,
• wherein the horizontal portion further includes a lower horizontal portion extending in the plane direction opposite to the upper horizontal portion from the lower end of the vertical portion, and the lower horizontal portion is layered in the height direction with the other one of the source electrode and the drain electrode, and does not overlap in the height direction with the gate electrode,
• wherein the gate electrode is further formed thereon with a hard film having an etching rate lower than an etching rate of the gate electrode, and
• wherein the hard film is used as a mask for forming the vertical plane of the gate electrode.