Phase tracking and correction architecture
AssigneeQUALCOMM Incorporated
InventorsGang Liu, Xiaotie Wu, Razak Hossain, Marco Zanuso, Yiwu Tang
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Abstract
Aspects described herein include devices and methods for phase tracking and correction using sampling. One aspect includes a wireless communication apparatus having an analog 1-bit sampler configured to sample a phase locked loop (PLL) output signal using a PLL reference clock to generate 1-bit samples and a digital phase computation and control circuit configured to receive the 1-bit samples from the analog 1-bit sampler and apply phase corrections to the PLL based on a phase error derived from the 1-bit samples.
Claims28
A wireless communication apparatus comprising:
- an analog sampler and 1-bit comparator configured to sample a phase locked loop (PLL) output signal from a PLL using a PLL reference clock to generate 1-bit samples, the PLL comprising a PLL output coupled to the analog sampler and 1-bit comparator to provide the PLL output signal to a signal buffer of the analog sampler and 1-bit comparator, wherein the PLL reference clock is connected to a PLL reference clock buffer of the analog sampler and 1-bit comparator;
- and
- a digital phase control circuit configured to receive the 1-bit samples from the analog sampler and 1-bit comparator and apply phase corrections to the PLL based on a phase error derived from the 1-bit samples.
A method comprising:
- determining a phase error threshold;
- calculating a phase error value using a plurality of 1-bit samples from a first circuit including an analog phase sample circuitry and a digital control circuitry, wherein the first circuit is coupled to an output of phase lock loop (PLL) circuitry and a reference clock of a wireless communication device, wherein the digital control circuitry comprises a first phase accumulator and a second phase accumulator, and wherein calculating the phase error value comprises calculating the phase error value based on the plurality of 1-bit samples and phase accumulation values from the first phase accumulator and the second phase accumulator;
- and
- applying a phase correction to the PLL circuitry based on an output of the digital control circuitry if the phase error value is greater than the phase error threshold.
A method comprising:
- determining a phase error threshold;
- calculating a phase error value using a plurality of 1-bit samples from a first circuit including an analog phase sample circuitry and a digital control circuitry, wherein the first circuit is coupled to an output of phase lock loop (PLL) circuitry and a reference clock of a wireless communication device;
- and
- applying a phase correction to the PLL circuitry based on an output of the digital control circuitry if the phase error value is greater than the phase error threshold,
- wherein determining the phase error threshold comprises:
- selecting an operational setup state among a single measurement state, a tracking measurement state, and a continuous measurement state;
- and
- calculating corresponding phase error values for a calculation period based on the operational setup state.
Dependencies are inferred from the claim text.