Analog-to-digital converter (ADC) having linearization circuit with reconfigurable lookup table (LUT) memory and calibration options

A circuit comprising:

• a multiplexer having a first input and a second input and an output, the multiplexer configured to receive an analog input signal at the first input;
• an analog-to-digital converter (ADC) having an input and an output, the input of the ADC coupled to the output of the multiplexer;
• a memory circuit having an input and an output, the input of the memory circuit coupled to the output of the ADC, the memory circuit having a first look-up table (LUT) and a second LUT;
• a calibration control circuit coupled to the multiplexer, the ADC and the memory circuit;
• and
• a digital-to-analog converter (DAC) having an input and an output, the input of the DAC coupled to the calibration control circuit and the output of the DAC coupled to the second input of the multiplexer, wherein the memory circuit is configured to:
• store a first data in the first LUT based on a first ramp signal applied to the ADC by the DAC;
• store a second data in the second LUT based on a second ramp signal applied to the ADC by the DAC;
• store an updated calibration data in one of the first LUT and the second LUT, the updated calibration data obtained from the first data and the second data;
• and
• generate a digital output at the output of the memory circuit based on the analog input signal and the updated calibration data.

A method comprising:

• providing multiple ramp signals to an analog-to-digital converter (ADC);
• storing an initial calibration data, in a compressed format, generated by the ADC corresponding to the multiple ramp signals in a memory circuit;
• converting the initial calibration data from the compressed format to an uncompressed format;
• generating an updated calibration data based on the initial calibration data in the uncompressed format;
• replacing the initial calibration data with the updated calibration data in the memory circuit;
• providing an analog input signal to the ADC to generate a first digital output;
• and
• generating a second digital output at an output of the memory circuit based on the updated calibration data and the first digital output.