Data reception device based on low-power digital delay-locked loop having skew correction function
AssigneeRamschip, Inc.
InventorsBong-Joon Lee, Jae-Gan Ko
Life of this patent
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Abstract
A data reception device includes a reference clock generation unit including a first DCDL, a phase detection circuit, and a digital loop filter, and receiving an input clock signal CK0 and outputting the input clock signal and a first phase clock signal CK90 having a phase difference of 90 degrees with respect to the input clock signal; and a data sampling unit including a second DCDL that receives a data signal DI, the input clock signal, and the first phase clock signal, and delays the data signal, and sampling and outputting a data value of the data signal at an edge of the input clock signal, thereby remarkably reducing an amount of power consumption used for skew correction.
Claims8
A data reception device based on a low-power digital delay-locked loop having a skew correction function, the device comprising:
- a reference clock generation unit comprising a first digitally-controlled delay line (DCDL), a phase detection circuit, and a digital loop filter, and receives an input clock signal CK0 and outputs the input clock signal and a first phase clock signal CK90 having a phase difference of 90 degrees with respect to the input clock signal;
- and
- a data sampling unit comprising a second DCDL that receives a data signal DI and delays the data signal DI, wherein the data sampling unit receives the input clock signal, and the first phase clock signal, and samples and outputs a data value of the data signal at an edge of the input clock signal,
- wherein an operation section of the data sampling unit comprises:
- a first section operating in a skew correction value measurement mode that finds a skew correction setting value of the second DCDL that delays the data signal so that a data value transition point of the data signal corresponds to an edge of the first phase clock signal;
- and
- a second section operating in a normal mode that samples, at the edge of the input clock signal CK0, the data value of the data signal delayed by the second DCDL in which the skew correction setting value is set.
Dependencies are inferred from the claim text.