Superconducting serial-to-parallel converter system
AssigneeNorthrop Grumman Systems Corporation
InventorsJames R. Medford, Kurt Pleim, Sean Ashley Lindsay
Life of this patent
Estimating the term…
Abstract
One example includes a superconducting serial-to-parallel converter system. The system includes a plurality of serial-input-parallel-output (SIPO) cells arranged in a sequence between a first SIPO cell and a last SIPO cell. Each of the SIPO cells is configured to convert a plurality of serial superconducting bits of a serial data stream into a set of parallel superconducting bits in response to an enable pulse. The enable pulse is provided through the sequence of SIPO cells from the first SIPO cell to the last SIPO cell based on the clock signal. The serial data stream is provided through the sequence of the SIPO cells from the last SIPO cell to the first SIPO cell based on a clock signal.
Claims20
A superconducting serial-to-parallel converter system comprising a plurality of serial-input-parallel-output (SIPO) cells arranged in a sequence between a first SIPO cell and a last SIPO cell, wherein each of the SIPO cells is configured to convert a plurality of serial superconducting bits of a serial data stream into a set of parallel superconducting bits in response to an enable pulse, wherein the serial data stream is provided through the sequence of the SIPO cells from the last SIPO cell to the first SIPO cell based on a clock signal, wherein the enable pulse is provided through the sequence of SIPO cells from the first SIPO cell to the last SIPO cell based on the clock signal.
A method for converting superconducting pulses from a serial data stream to parallel data bits, the method comprising:
- providing an enable pulse to a first serial-input-parallel-output (SIPO) cell of a serial sequence of the SIPO cells;
- providing the serial data stream comprising a plurality of serial superconducting bits to a last SIPO cell of the serial sequence of SIPO cells;
- providing a clock signal to the serial sequence of SIPO cells, such that the serial data stream propagates from the last SIPO cell to the first SIPO cell and the enable pulse propagates from the first SIPO cell to the last SIPO cell;
- and
- providing a plurality of logic AND operations in each of the SIPO cells between the enable pulse and each of the serial superconducting bits to provide a set of parallel superconducting bits from each of the SIPO cells.
A superconducting serial-to-parallel converter system comprising a plurality of serial-input-parallel-output (SIPO) cells arranged in a sequence between a first SIPO cell and a last SIPO cell, wherein an enable pulse is provided through the sequence of SIPO cells from the first SIPO cell to the last SIPO cell based on a clock signal, wherein a serial data stream is provided through the sequence of the SIPO cells from the last SIPO cell to the first SIPO cell based on a clock signal, wherein each of the SIPO cells comprises:
- a serial data path comprising a set of serial data Josephson transmission lines (JTLs) configured to propagate the serial superconducting bits along the serial data path through the respective one of the SIPO cells based on the clock signal;
- an enable path comprising a set of enable JTLs configured to propagate the enable pulse along the enable path through the respective one of the SIPO cells based on the clock signal in a direction opposite the propagation of the serial superconducting bits;
- a plurality of AND-gates configured to provide a logic AND operation between the enable pulse and each of a set of serial superconducting bits of the serial data stream to generate a corresponding set of parallel superconducting bits;
- and
- a set of delay JTLs configured to delay at least one of the parallel superconducting bits relative to at least one other of the parallel superconducting bits, such that the set of parallel superconducting bits are provided from the respective one of the SIPO cells concurrently.
Dependencies are inferred from the claim text.