Switching circuit
AssigneeRohm Co., Ltd.
InventorShinya Karasawa
Life of this patent
Estimating the term…
Abstract
A switching controller generates control pulses for specifying on/off states of a first transistor and a second transistor. One end of a capacitor is coupled to a switching node. A constant voltage is applied to the other end of the capacitor via a rectifier element. A dead time controller controls a delay time between adjacent edges of the first control pulse and the second control pulse according to a sensing voltage across both ends of the capacitor.
Claims22
A switching circuit comprising:
- a first transistor and a second transistor;
- a switching node, wherein a high-level voltage occurs at the switching node during a period in which the first transistor is turned on and the second transistor is turned off, a low-level voltage occurs at the switching node during a period in which the first transistor is turned off and the second transistor is turned on, and a negative voltage occurs at the switching node during a period in which both the first transistor and the second transistor are turned off;
- a capacitor structured such that a first end thereof is coupled to the switching node;
- a rectifier element structured to apply a constant voltage to a second end of the capacitor;
- a switching controller structured to generate a first control pulse and a second control pulse for specifying on/off states of the first transistor and the second transistor;
- a first gate driver structured to drive the first transistor according to the first control pulse;
- a second gate driver structured to drive the second transistor according to the second control pulse;
- a dead time controller structured to control a delay time between edges of the first control pulse and the second control pulse according to a sensing voltage across both ends of the capacitor;
- and
- a discharge circuit coupled to the capacitor, and structured to discharge a charge stored in the capacitor in a period in which the first transistor is turned on.
A control circuit for a switching power supply, wherein a switching circuit comprises:
- a first transistor and a second transistor;
- a switching node, wherein a high-level voltage occurs at the switching node during a period in which the first transistor is turned on and the second transistor is turned off, a low-level voltage occurs at the switching node during a period in which the first transistor is turned off and the second transistor is turned on, and a negative voltage occurs at the switching node during a period in which both the first transistor and the second transistor are turned off;
- a capacitor structured such that a first end thereof is coupled to the switching node;
- a rectifier element structured to apply a constant voltage to a second end of the capacitor;
- a first gate driver structured to drive the first transistor according to a first control pulse;
- a second gate driver structured to drive the second transistor according to a second control pulse;
- and
- a discharge circuit structured to discharge a charge stored in the capacitor in a period in which the first transistor is turned on,
- and wherein the control circuit comprises:
- a switching controller structured to generate the first control pulse and the second control pulse for specifying on/off states of the first transistor and the second transistor;
- and
- a dead time controller structured to control a delay time between adjacent edges of the first control pulse and the second control pulse according to a sensing voltage across both ends of the capacitor.
A switching circuit comprising:
- a first transistor and a second transistor;
- a switching node, wherein a high-level voltage occurs at the switching node during a period in which the first transistor is turned on and the second transistor is turned off, a low-level voltage occurs at the switching node during a period in which the first transistor is turned off and the second transistor is turned on, and a negative voltage occurs at the switching node during a period in which both the first transistor and the second transistor are turned off;
- a capacitor structured such that a first end thereof is coupled to the switching node;
- a rectifier element structured to apply a constant voltage to a second end of the capacitor;
- a switching controller structured to generate a first control pulse and a second control pulse for specifying on/off states of the first transistor and the second transistor;
- a first gate driver structured to drive the first transistor according to the first control pulse;
- a second gate driver structured to drive the second transistor according to the second control pulse;
- a dead time controller structured to control a delay time of at least one from among the first gate driver and the second gate driver according to a sensing voltage across both ends of the capacitor;
- and
- a discharge circuit coupled to the capacitor, and structured to discharge a charge stored in the capacitor in a period in which the first transistor is turned on.
A gate driver circuit for a switching power supply, wherein the switching power supply comprises:
- a first transistor and a second transistor;
- a switching node, wherein a high-level voltage occurs at the switching node during a period in which the first transistor is turned on and the second transistor is turned off, a low-level voltage occurs at the switching node during a period in which the first transistor is turned off and the second transistor is turned on, and a negative voltage occurs at the switching node during a period in which both the first transistor and the second transistor are turned off;
- a capacitor structured such that a first end thereof is coupled to the switching node;
- a rectifier element structured to apply a constant voltage to a second end of the capacitor;
- and
- a switching controller structured to generate a control signal for specifying a duty cycle of each of the first transistor and the second transistor such that an electrical state of the switching power supply approaches a target state,
- and wherein the gate driver circuit comprises:
- a pulse generating unit structured to generate a first control pulse and a second control pulse each having a duty cycle that corresponds to the control signal;
- a first gate driver structured to drive the first transistor according to the first control pulse;
- a second gate driver structured to drive the second transistor according to the second control pulse;
- a dead time controller structured to control a delay time between adjacent edges of the first control pulse and the second control pulse according to a sensing voltage across both ends of the capacitor;
- and
- a discharge circuit structured to discharge a charge stored in the capacitor in a period in which the first transistor is turned on.
Dependencies are inferred from the claim text.