Method and structure for determining an overlay error
AssigneeImec Vzw
InventorsWaikin Li, Zheng Tao, Min-Soo Kim
Life of this patent
Estimating the term…
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AssigneeImec Vzw
InventorsWaikin Li, Zheng Tao, Min-Soo Kim
Estimating the term…
A semiconductor structure includes a device area that includes a first structure in a first layer having a top surface above a top surface of the first layer, and a second structure in a second layer on top of the first layer, where the first structure is pinned in the second structure; an overlay metrology area for optically evaluating an overlay error between the second and first structure, including: a third structure in the first layer, having a top surface above the top surface of the first layer, a fourth structure in the second layer, where the combination of the third and fourth structures mimics the combination of the first structure and the second structures, and a fifth structure in the first layer, for use as a reference structure.
A semiconductor structure comprising:
A method comprising:
Dependencies are inferred from the claim text.