Chip-last wafer-level fan-out with optical fiber alignment structure
AssigneeAyar Labs, Inc.
InventorRoy Edward Meade
Life of this patent
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AssigneeAyar Labs, Inc.
InventorRoy Edward Meade
Estimating the term…
A redistribution layer is formed on a carrier wafer. A cavity is formed within the redistribution layer. An electro-optical die is flip-chip connected to the redistribution layer. A plurality of optical fiber alignment structures within the electro-optical die is positioned over and exposed to the cavity. Mold compound material is disposed over the redistribution layer and the electro-optical die. A residual kerf region of the electro-optical die interfaces with the redistribution layer to prevent mold compound material from entering into the optical fiber alignment structures and the cavity. The carrier wafer is removed from the redistribution layer. The redistribution layer and the mold compound material are cut to obtain an electro-optical chip package that includes the electro-optical die. The cutting removes the residual kerf region from the electro-optical die to expose the plurality of optical fiber alignment structures and the cavity at an edge of the electro-optical chip package.
An electro-optical chip package, comprising:
An electro-optical chip package, comprising:
An electro-optical chip package, comprising:
Dependencies are inferred from the claim text.