Forming interconnect structures in semiconductor devices

A method of forming a semiconductor structure, comprising:

• forming a first metallization layer over a substrate;
• patterning the first metallization layer to form isolation trenches in the first metallization layer;
• forming dielectric separators in the isolation trenches to form a first conductive feature sandwiched between the dielectric separators;
• depositing an etch-stop layer (ESL) stack on the first metallization layer and on the dielectric separators, the ESL stack having a continuous planar top surface above top surfaces of both the first conductive feature and the dielectric separators;
• depositing a first interlayer dielectric (ILD) layer over the ESL stack;
• forming a patterned ESL over the first ILD layer, wherein the patterned ESL has an opening directly above the first conductive feature, and the opening is wider than the first conductive feature;
• depositing a second ILD layer over the patterned ESL, such that the second ILD layer extends through the opening of the patterned ESL to contact the first ILD layer;
• forming a patterned hard mask (HM) over the second ILD layer;
• forming a first trench that extends through the second ILD layer and the first ILD layer but not through the ESL stack;
• after forming the first trench, forming a second trench to selectively remove the ESL stack to expose the first conductive feature, wherein the forming of the second trench includes performing alternating wet and dry etch processes, and one of the wet etch processes removes portions of a dielectric cap layer exposed in the second trench and surrounding the dielectric separators;
• depositing a conductive layer in the first trench and the second trench;
• and
• planarizing the conductive layer to form a via contact in the first ILD layer and a second metallization layer in the second ILD layer, wherein the via contact interconnects the second metallization layer to the first metallization layer.

A method of forming a semiconductor structure, comprising:

• forming a first conductive layer over a substrate;
• patterning the first conductive layer to form a first conductive feature and a first trench adjacent to the first conductive feature;
• forming a dielectric layer in the first trench, the dielectric layer protrudes from a top surface of the first conductive feature;
• forming an etch-stop layer (ESL) stack over the first conductive feature, wherein the ESL stack includes a material that continuously conform to a top surface of the first conductive feature and top and sidewall surfaces of the dielectric layer, wherein the ESL stack has a continuous planar top surface spanning above the first conductive feature and the dielectric layer;
• forming a first interlayer dielectric (ILD) layer over the ESL stack;
• forming a patterned ESL over the first ILD layer, wherein the patterned ESL includes a first opening;
• forming a second ILD layer over the patterned ESL, thereby filling the first opening;
• forming a patterned hard mask (HM) over the second ILD layer, wherein the patterned HM includes a second opening, and wherein the second opening is wider than the first opening;
• forming a trench by first etching through the second ILD layer and the first ILD layer using the patterned HM and patterned ESL as etch masks and the ESL stack as an etch stop, wherein the first etching includes performing a single dry etch process;
• after forming the trench, extending the trench by second etching through the ESL stack, thereby exposing the top surface of the first conductive feature, wherein the second etching includes performing alternating wet and dry etch processes;
• and
• depositing a second conductive layer in the trench, thereby forming a second conductive feature in the first ILD layer and a third conductive feature in the second ILD layer, wherein the second conductive feature interconnects the first conductive feature to the third conductive feature, and wherein portions of sidewalls of the third conductive feature are defined by the second ILD layer.