Technologies for current biasing for three-dimensional crosspoint memory cells
AssigneeIntel Corporation
InventorsJonathan Y. Wang, Yasir Mohsin Husain, Ashraf B. Islam
Life of this patent
Estimating the term…
Abstract
Techniques for current biasing for memory cells are disclosed. In the illustrative embodiment, a source follower sets a voltage on a bitline of a memory cell. The current through the source follower is limited by a current mirror in series with the source follower. When additional current is required that the source follower cannot supply, a feedback transistor is activated to provide additional current. Additionally, in some embodiments, the current through the feedback transistor is copied to a current mirror, and the copied current is used to sense the state of the memory cell.
Claims21
A memory die comprising:
- a plurality of three-dimensional crosspoint memory cells;
- and
- a voltage regulator to drive a bitline of the plurality of three-dimensional crosspoint memory cells, the voltage regulator to drive the bitline comprising:
- a first PMOS transistor, wherein a source of the first PMOS transistor is connected to a positive rail;
- an NMOS transistor, wherein a drain of the NMOS transistor is connected to a drain of the first PMOS transistor, wherein a source of the NMOS transistor is connected to the bitline;
- and
- a second PMOS transistor, wherein a source of the second PMOS transistor is connected to the positive rail, wherein a drain of the second PMOS transistor is connected to the source of the NMOS transistor, wherein a gate of the second PMOS transistor is connected to the drain of the first PMOS transistor and the drain of the NMOS transistor.
A memory die comprising:
- a plurality of three-dimensional crosspoint memory cells;
- sensor circuitry comprising:
- a current mirror PMOS transistor, wherein a source of the current mirror PMOS transistor is connected to a positive rail, wherein a gate of the current mirror PMOS transistor is connected to a drain of a second PMOS transistor that is to provide current to a memory cell of the plurality of three-dimensional crosspoint memory cells;
- and
- one or more digital logic gates to sense a voltage at a drain of the current mirror PMOS transistor based on a state of the memory cell;
- and
- a voltage regulator to drive a bitline of the plurality of three-dimensional crosspoint memory cells, the voltage regulator to drive the bitline comprising:
- a third PMOS transistor, wherein a source of the third PMOS transistor is connected to the positive rail;
- an NMOS transistor, wherein a drain of the NMOS transistor is connected to a drain of the third PMOS transistor, wherein a source of the NMOS transistor is connected to the bitline;
- and
- the second PMOS transistor, wherein a source of the second PMOS transistor is connected to the positive rail, wherein a drain of the second PMOS transistor is connected to the source of the NMOS transistor, wherein a gate of the second PMOS transistor is connected to the drain of the third PMOS transistor and the drain of the NMOS transistor.
A memory die comprising:
- a plurality of three-dimensional crosspoint memory cells;
- and
- means for providing a demarcation voltage to a bitline of the plurality of three-dimensional crosspoint memory cells;
- means for limiting current through the means for providing the demarcation voltage;
- means for providing additional current to the bitline in response to sensing that current through the means for providing the demarcation voltage is limited;
- and
- means for sensing current through the means for providing additional current to the bitline.
Dependencies are inferred from the claim text.