Field programmable gate array (FPGA) based online 3D bin packing

A pipe-lined Field Programmable Gate Array (FPGA) implemented system, configured by the instructions to:

• receive a plurality of inputs from a plurality of sources, wherein the plurality of inputs is associated with a plurality of boxes, and a Long-Distance Container (LDC) in which the plurality of boxes is to be packed, wherein the plurality of inputs comprises:
• a plurality of box dimensions for each box from the plurality of boxes, represented by a length (I), a breadth (b) and a height (h);
• a plurality of coordinates within the LDC;
• and
• a 2D-Array representation of the LDC where each element of the 2D array comprises a value equivalent to the height (h) of the plurality of boxes packed at a coordinate from the plurality of coordinates;
• identify a list of feasible alignments for each of the plurality of boxes from the plurality of boxes, in the LDC, by iterating through the plurality of coordinates, via the one or more hardware processors, wherein the list of feasible alignments is a list of coordinates within the LDC where the box can be placed, where the iteration comprising:
• performing a dimension eligibility check for a coordinate from the plurality of coordinates based on a parallel processing technique;
• and
• performing a surface eligibility check and a physical stability check for the coordinate based on a parallel comparator technique;
• determine a set of features for each feasible alignment from the list of feasible alignments, via the one or more hardware processors, based on a set of parallel processing technique, wherein the set of features comprises a LDC state, a border state, and an aggregate state;
• and
• identify a final alignment for each of the plurality of boxes within the LDC, based on the set of features and the list of feasible alignments, via the one or more hardware processors, using a pre-trained DQN inference layer wherein the pre-trained DQN inference layer is pre-trained using a generic purpose processor.

One or more non-transitory machine readable information storage mediums comprising one or more instructions which when executed by one or more hardware processors cause:

• receiving a plurality of inputs from a plurality of sources, wherein the plurality of inputs is associated with a plurality of boxes, and a Long-Distance Container (LDC) in which the plurality of boxes is to be packed, wherein the plurality of inputs comprises:
• a plurality of box dimensions for each box from the plurality of boxes, represented by a length (I), a breadth (b) and a height (h);
• a plurality of coordinates within the LDC;
• and
• a 2D-Array representation of the LDC where each element of the 2D array comprises a value equivalent to the height (h) of the plurality of boxes packed at a coordinate from the plurality of coordinates;
• identifying a list of feasible alignments for each of the plurality of boxes from the plurality of boxes, in the LDC, by iterating through the plurality of coordinates, via the one or more hardware processors, wherein the list of feasible alignments is a list of coordinates within the LDC where the box can be placed, where the iteration comprising:
• performing a dimension eligibility check for a coordinate from the plurality of coordinates based on a parallel processing technique;
• and
• performing a surface eligibility check and a physical stability check for the coordinate based on a parallel comparator technique;
• determining a set of features for each feasible alignment from the list of feasible alignments, via the one or more hardware processors, based on a set of parallel processing technique, wherein the set of features comprises a LDC state, a border state, and an aggregate state, and
• identifying a final alignment for each of the plurality of boxes within the LDC, based on the set of features and the list of feasible alignments, via the one or more hardware processors, using a pre-trained DQN inference layer wherein the pre-trained DQN inference layer is pre-trained using a generic purpose processor.