Universal synchronous FIFO IP core for field programmable gate arrays
AssigneeRaytheon Company
InventorsVivian V. Huynh-Romine, John Mui, Howard K. Luu
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Abstract
A field programmable gate array (FPGA) device including a configuration interface arranged to receive configuration data from an FPGA programmer. The FPGA device includes a plurality of random access memory (RAM) types, including a first RAM type and a second RAM type, arranged to store the configuration or image data. The FPGA device also includes a FIFO IP core arranged to implement a FIFO function in a plurality of different FPGA platforms. The FIFO IP core is: i) configured to implement the FIFO in the FPGA device based on the configuration data, and ii) configurable to store the configuration data in one or both of the first RAM type and the second RAM type.
Claims20
A field programmable gate array (FPGA) device comprising:
- a configuration interface arranged to receive data from an FPGA programmer;
- a plurality of random access memory (RAM) types, including a first RAM type and a second RAM type, arranged to store the data;
- and
- a first-in first-out (FIFO) intellectual property (IP) core arranged to implement a FIFO function in a plurality of different FPGA platforms, the FIFO IP core:
- i) implements the FIFO function in the FPGA device based on the data, and ii) stores portions of the data such that different first and second respective portions of the data are stored in both the first RAM type and the second RAM type, such that the first portion is stored in the first RAM type and the second portion is stored in the second RAM type, the FPGA device including a plurality of parameters in the data, the plurality of parameters including a RAM type parameter for selecting a storage location of the FIFO IP core within the plurality of RAM types by setting the RAM type parameter to numerical values, where the RAM type parameter comprises a different numerical value for each of the plurality of RAM types.
A method for configuring a field programmable gate array (FPGA) device implementing a universal first-in first-out (FIFO) intellectual property (IP) core comprising:
- configuring the universal FIFO IP core to implement a FIFO function in the FPGA device;
- interfacing an FPGA programmer, via a communications interface, with the FPGA device;
- imaging the FPGA device with data arranged to implement the universal FIFO IP core in the FPGA device, the universal FIFO IP core configured to implement the FIFO function in a plurality of FPGA platforms;
- and
- storing portions of the data such that different first and second respective portions of the data are stored in both a first RAM type and a second RAM type in the FPGA device, such that the first portion is stored in the first RAM type and the second portion is stored in the second RAM type, the FPGA device including a plurality of parameters in the data, the plurality of parameters including a RAM type parameter for selecting storage locations of the universal FIFO IP core within the first RAM type or the second RAM type by setting the RAM type parameter to a numerical value, where the RAM type parameter comprises a different numerical value for each of the first RAM type and second RAM type.
A non-transient computer readable medium containing program instructions for causing a computer to implement a universal first-in first-out (FIFO) intellectual property (IP) core in a field programmable gate array (FPGA) device comprising operations:
- configuring the universal FIFO IP core to implement a FIFO function in the FPGA device based on configuration data;
- interfacing with an FPGA programmer, via a communications interface, by the FPGA device;
- imaging the FPGA device with the configuration data arranged to implement the universal FIFO IP core in the FPGA device, the universal FIFO IP core configured to implement a FIFO function in a plurality of FPGA platforms;
- and
- storing portions of the configuration data such that first and second different portions of the data are stored in both a first RAM type and a second RAM type in the FPGA device, such that the first portion is stored in the first RAM type and the second portion is stored in the second RAM type, the FPGA device including a plurality of parameters in the configuration data, the plurality of parameters including a RAM type parameter for selecting storage locations of the FIFO IP core within the first RAM type and the second RAM type, where the RAM type parameter comprises a different numerical value for each of the first RAM type and the second RAM type.
Dependencies are inferred from the claim text.