Memory failure prediction and mitigation

A system comprising:

• a memory controller;
• and
• a memory device comprising an array of memory cells;
• wherein the controller is configured to:
• receive correctable error information based on data from a data pin of the memory device;
• based on the correctable error information, identify one or more memory cells of the array that comprise data with correctable errors;
• identify a first addressable portion of the memory device that corresponds to multiple cells in the array and comprises the data with correctable errors;
• and
• offline one or more memory pages corresponding to the first addressable portion of the memory device, wherein:
• the controller is configured to receive the correctable error information over time and count a number of correctable errors associated with respective ones of the memory cells, and
• the controller is configured to use the count to determine when to offline the one or more memory pages of the memory device.

A non-transitory processor-readable storage medium, the processor-readable storage medium including instructions that when executed by a processor circuit, cause the processor circuit to:

• receive information about correctable errors from a data input/output (DQ) pin of a memory device;
• identify memory cell locations in the memory device corresponding to the received information about the correctable errors;
• identify a failure pattern using information about the memory cell locations;
• determine a count of correctable errors for each of the memory cell locations, wherein identifying the failure pattern includes using the count;
• and
• in response to identifying the failure pattern, offline one or more addressable memory pages corresponding to the memory cell locations in the memory device.