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US 12,511,124 B2Granted
Static identifications in object-based memory access
AssigneeMicron Technology, Inc.
InventorSteven Jeffrey Wallach
Life of this patent
Estimating the term…
Abstract
A computer system having an address system of a first predetermined width in which each address of the first predetermined width in the address system includes a first portion identifying an object and a second portion identifying an offset relative to the object, where a static identifier for the first portion is predetermined to identify an address space having a second predetermined width that is smaller than the first predetermined width, or a space of kernel objects.
Claims20
A computer system, comprising:
- a register of a first predetermined width, the register storing an address having:
- a first portion identifying an object;
- and
- a second portion identifying an offset relative to the object, wherein the offset is utilized for loading an instruction from a memory location;
- and
- an execution unit configured to load the instruction using the offset and execute the instruction using the address in accessing memory;
- wherein the first portion has a static identifier used in executing the instruction and configured to identify a predetermined object type of the object to facilitate adjusting of at least one operation conducted by a processor in accordance with the predetermined object type.
4 more elements
A method, comprising:
- receiving, in a processor, a first address in a memory address space having a first predetermined width;
- determining, by the processor, an identifier predefined to represent the memory address space and configured to identify a predetermined object type of an object associated with the first address to facilitate adjusting of at least one operation conducted by the processor in accordance with the predetermined object type;
- and
- combining, by the processor, the predefined identifier and the first address to generate a second address having a second predetermined width larger than the first predetermined width, wherein the second address has an object identifier portion and a byte offset portion, and the object identifier portion of the second address contains the predefined identifier representing the memory address space and the byte offset portion of the second address corresponds to the first address.
1 more element
A computer system, comprising:
- a memory address system of a first predetermined width in which each memory address of the first predetermined width in the memory address system includes an object identifier portion and an offset portion,
- wherein the offset is utilized for loading an instruction from a memory location,
- wherein an execution unit in the computer system is configured to load the instruction using the offset and execute the instruction using a memory address of the memory address system in accessing memory.
Dependencies are inferred from the claim text.