Packet routing between memory devices and related apparatuses, methods, and memory systems

A method for interconnecting host devices and one or more memory devices, the host devices each including an interface to communicate read and write request packets over respective packetized links, the one or more memory devices each including multiple memory dies and an interface to receive and respond to the read and write request packets over the respective packetized links, respective ones of the read and write request packets including at least a packet header, the method comprising:

• receiving routing configuration information at devices of a routing system, the devices of the routing system interconnected in a routing topology, respective ones of the devices identified by respective device IDs, the respective ones of the devices comprising a crossbar switch, link interface controllers, and link interfaces;
• and
• routing, via the devices of the routing system, the read and write request packets and response packets between the host devices and respective memory device destinations over the respective packetized links based on the routing configuration information, the respective ones of the devices using the crossbar switch either to accept or to pass a respective read or write request packet to an appropriate adjacent device based on the respective device ID included in the packet header, respective ones of the read and write request packets addressed to a respective physical address included in the packet header, the respective physical address including a physical memory address in a respective memory die of the respective memory device destination.

An interconnect system comprising:

• host devices including a first host device and a second host device, the first host device including a first interface to communicate a read request packet having a packet header over a first packetized link, the second host device including a second interface to communicate a read request packet having a packet header over a second packetized link;
• semiconductor memory devices including a first semiconductor memory device and a second semiconductor memory device, the first semiconductor memory device including first multiple memory dies and a first interface to receive and respond to the read request packet from the first host device over the first packetized link, the second semiconductor memory device including second multiple memory dies and a second interface to receive and respond to the read request packet from the second host device over the second packetized link;
• and
• a device of a routing system, the device of the routing system to route the read request packets and response packets between the host devices and respective semiconductor memory device destinations, the device identified by a device ID, the device comprising a crossbar switch, link interface controllers, and link interfaces, the device using the crossbar switch to route the read request packets via the routing system based on the device ID included in the packet header, the link interfaces of the device including a first interface of the device to connect to the first interface of the first host device, a second interface of the device to connect to the second interface of the second host device, a third interface of the device to connect to the first interface of the first semiconductor memory device, and a fourth interface of the device to connect to the second interface of the second semiconductor memory device,
• wherein the read request packet from the first host device is addressed to a respective physical address included in the packet header, the respective physical address including a respective physical memory address in a respective memory die of the first semiconductor memory device, and
• wherein the read request packet from the second host device is addressed to a respective physical address included in the packet header, the respective physical address including a respective physical memory address in a respective memory die of the second semiconductor memory device.