Semiconductor device and method

A semiconductor device comprising:

• a semiconductor substrate, the semiconductor substrate having a first semiconductor structure protruding from the semiconductor substrate and above a first isolation structure in a first region and a second semiconductor structure protruding from the semiconductor substrate and above a second isolation structure in a second region, a top surface of the semiconductor substrate corresponding to a top surface of the first semiconductor structure;
• a first nanostructure in the first region on the semiconductor substrate, the first nanostructure disposed directly above the first semiconductor structure;
• a first gate structure surrounding the first nanostructure;
• a first source/drain region adjacent the first gate structure and the first nanostructure, wherein a bottom surface of the first source/drain region extends into the top surface of the first semiconductor structure to a first depth below the top surface of the semiconductor substrate in a first direction perpendicular to a major surface of the semiconductor substrate;
• a second nanostructure in the second region on the semiconductor substrate, the second nanostructure disposed directly above the second semiconductor structure;
• a second gate structure surrounding the second nanostructure;
• a second source/drain region adjacent the second gate structure and the second nanostructure, wherein a bottom surface of the second source/drain region extends into the top surface of the second semiconductor structure to a second depth below the top surface of the semiconductor substrate in the first direction, wherein the first depth is greater than the second depth;
• a first inner spacer along a side surface of the first nanostructure between the first nanostructure and the first source/drain region, wherein the first inner spacer is silicon;
• and
• a second inner spacer along a side surface of the second nanostructure between the second nanostructure and the second source/drain region, wherein the second inner spacer comprises a material having a dielectric constant less than 3.5.

A semiconductor device comprising:

• a first nanostructure on a semiconductor substrate in a first region of the semiconductor substrate, the first nanostructure comprising a first semiconductor material, the semiconductor substrate including a topmost surface;
• a fin structure extending from the semiconductor substrate in a second region of the semiconductor substrate, the fin structure comprising a second semiconductor material, wherein the second semiconductor material extends continuously and uninterrupted from the top surface of semiconducting material of the semiconductor substrate to a topmost surface of the fin structure, the topmost surface of the fin structure being level with the topmost surface of the first nanostructure, the fin structure including a channel region;
• a gate structure overlying the channel region;
• a first isolation structure laterally surrounding a base of the fin structure, the first isolation structure contacting sidewall surfaces of the fin structure;
• a first source/drain region adjacent the first nanostructure, wherein a bottommost surface of the first source/drain region is a first distance below the topmost surface of the first nanostructure;
• a second source/drain region adjacent the channel region, wherein a bottom surface of the second source/drain region is a second distance below the topmost surface of the fin structure, the first distance being greater than the second distance;
• and
• a first inner spacer in contact with the first nanostructure and the first source/drain region, wherein the first inner spacer is formed of silicon.