Semiconductor device

A semiconductor device comprising:

• a semiconductor substrate including a drift layer of a first conductivity type;
• the semiconductor device including an IGBT region and a diode region that are disposed with a boundary region interposed between the IGBT region and the diode region in a first direction in plan view;
• the semiconductor substrate having a first main surface, and a second main surface facing the first main surface;
• the IGBT region and the boundary region each including:
• a base layer of a second conductivity type that is formed on a first main surface side of the drift layer;
• a source layer of the first conductivity type that is formed on the first main surface side of the base layer;
• a first contact layer of the second conductivity type that is formed directly adjacent to the source layer on the first main surface side of the base layer, and has a higher concentration of impurities of the second conductivity type than the base layer;
• a collector layer of the second conductivity type that is formed on a second main surface side of the drift layer;
• and
• at least one active trench gate directly adjacent to the source layer that passes through the base layer from the first main surface to reach the drift layer and that extends in a second direction orthogonal to the first direction;
• the diode region including:
• an anode layer of the second conductivity type that is formed on the first main surface side of the drift layer;
• and
• a cathode layer of the first conductivity type that is formed on the second main surface side of the drift layer;
• and
• in plan view, the boundary region having an occupancy rate of the source layer per unit area, the occupancy rate being smaller than an occupancy rate of the source layer per unit area in the IGBT region,
• in plan view, the boundary region having an occupancy rate of the first contact layer per unit area, the occupancy rate being smaller than an occupancy rate of the first contact layer per unit area in the IGBT region,
• each active trench gate is configured to be connectable to a gate drive voltage to form a channel in the respective base layer of the IGBT region and the boundary region,
• the source layer in the boundary region comprises plural source regions spaced from each other, and the source layer in the IGBT region comprises plural source regions spaced from each other, wherein along the second direction, the boundary region includes fewer of the source regions compared with the IGBT region, and
• in plan view, the first contact layer in the boundary region comprises plural first contact layers each spaced from each other by way of the base layer along the second direction.