High-density three-dimensional multilayer memory and fabrication method

A fabrication method of a high-density three-dimensional multilayer memory, comprising the following steps:

• firstly, forming a basic structure body:
• setting up a preset number of first conducting medium layers and insulating medium layers in such a manner that the first conducting medium layers and the insulating medium layers are alternately stacked on top of each other to form a basic structure body;
• secondly, grooving the basic structure body:
• forming a curve-shaped division groove penetrating from the top layer to the bottom layer of the basic structure body, and dividing the basic structure body into two staggered and separated interdigitated structures by the division groove;
• thirdly, forming a preset number of memory cell holes in the division groove, wherein an insulating medium is disposed between every two adjacent memory cell holes, a vertical electrode is set in the memory cell hole, and a memory medium layer is set between the vertical electrode and the interdigitated structure;
• the vertical electrode, the memory medium and the first conducting medium are made of materials meeting the requirements of a preset memory, and the memory is a PN junction type semiconductor memory or a Schottky semiconductor memory;
• and
• in the third step, before the memory medium is disposed, the fabrication method comprises the following step:
• placing a buffer region on the surface of a first conducting medium area on the inner wall of the division groove;
• wherein
• the third step comprises the following substeps:
• depositing and forming a buffer region on the surface of the first conducting medium layer on the inner wall of the division groove, wherein the conductive type of the buffer region is the same as that of the first conducting medium and the doping concentration of the buffer region is lower than that of the first conducting medium;
• filling the insulating medium in the division groove, etching the filled insulating medium to form the memory cell holes disposed along the division groove, and exposing the buffer region in the memory cell hole;
• depositing an insulating material on the inner wall of the memory cell hole as a memory medium to form a memory medium layer covering the inner wall of the memory cell hole, and then etching the memory medium layer at the bottom of the memory cell hole to expose an underlying circuit;
• disposing a vertical electrode in the memory cell hole;
• and
• the materials of the conducting medium layer, the middle medium layer and the vertical electrode layer meet one of the following conditions:
• the first conducting medium layer is a P-type semiconductor, and the vertical electrode layer is an N-type semiconductor;
• the first conducting medium layer is an N-type semiconductor, and the vertical electrode layer is a P-type semiconductor;
• and
• the first conducting medium layer is made of a semiconductor material meeting the requirement of a Schottky diode, and the vertical electrode is made of a metal meeting the requirement of the Schottky diode.