Resistive memory cell and associated cell array structure

A cell array structure comprising a first resistive memory cell, the first resistive memory cell comprising:

• a semiconductor substrate;
• a first-type well region formed under a surface of the semiconductor substrate;
• a first isolation structure formed in the first-type well region;
• a second-type well region formed in the first-type well region, wherein the second-type well region is located beside a first side of the first isolation structure;
• a first gate structure formed over a surface of the first-type well region and located beside a second side of the first isolation structure;
• a second gate structure formed over a surface of the second-type well region;
• a first second-type doped region and a second second-type doped region formed in the first-type well region, wherein the first second-type doped region and the second second-type doped region are located beside two opposite sides of the first gate structure;
• a third second-type doped region and a fourth second-type doped region formed in the second-type well region, wherein the third second-type doped region and the fourth second-type doped region are located beside two opposite sides of the second gate structure, wherein the third second-type doped region, the fourth second-type doped region and the second-type well region are collaboratively formed as a second-type merged region;
• a first conductor line connected with the first second-type doped region;
• a second conductor line connected with a conductive layer of the first gate structure;
• a third conductor line connected with the second second-type doped region and a conductive layer of the second gate structure;
• and
• a fourth conductor line connected with the second-type merged region.