Memory device including memory blocks different from each other

A memory device comprising:

• a memory cell array including a plurality of memory cells and divided into a plurality of blocks;
• a row decoder connected to the memory cell array through word lines;
• a page buffer connected to the memory cell array through bit lines;
• and
• a control logic circuit configured to control the memory cell array through the row decoder and the page buffer,
• wherein the memory cell array, the row decoder, and the page buffer are provided in a plurality of planes including a first plane and a second plane,
• wherein each of the memory cell array of the first plane and the memory cell array of the second plane includes main blocks and at least a first spare block, respectively,
• wherein the number of memory cells included in each spare block is less than the number of memory cells included in each of the main blocks,
• wherein the control logic circuit allocates a portion of the memory cells included in each spare block as active memory cells, and allocates remainder of the memory cells included in each spare block as non-active memory cells, and
• wherein for each spare block, the control logic circuit writes data to only the active memory cells.

A memory device comprising:

• a cell region in which a plurality of memory blocks are disposed, each of the memory blocks including gate electrode layers and insulating layers alternately stacked on a substrate, and channel structures extending in a first direction perpendicular to an upper surface of the substrate, and passing through the gate electrode layers and the insulating layers to be connected to the substrate, the first direction being a vertical direction;
• and
• a peripheral circuit region including a row decoder connected to the gate electrode layers and a page buffer connected to the channel structures,
• wherein the gate electrode layers in each of the memory blocks provide at least one ground selection line, a plurality of word lines, and a plurality of string selection lines, wherein the string selection lines are separated from each other in a second, horizontal, direction perpendicular to a first, horizontal, direction in which the string selection lines extend, and
• wherein, along the second direction, the number of the string selection lines included in each memory block of a first group of the memory blocks is different from the number of the string selection lines included in each memory block of a second group of the memory blocks.