A semiconductor structure, comprising a semiconductor device array, wherein the semiconductor device array comprises a plurality of semiconductor devices, each of the plurality of semiconductor devices comprises:
- a substrate;
- an active pillar array structure located on the substrate, the active pillar array structure comprising a plurality of active pillars arrayed in a second direction and a third direction, each of the plurality of active pillars extending in a first direction, the first direction being parallel to a substrate plane, the second direction being parallel to the substrate plane and perpendicular to the first direction, and the third direction being perpendicular to the substrate plane, wherein
- each of the plurality of active pillars comprises a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked sequentially in the second direction;
- a plurality of first word lines and a plurality of second word lines, the plurality of first word lines and the plurality of second word lines extending in the third direction, each column of the active pillars arranged in the third direction corresponding to a respective one of the plurality of first word lines and a respective one of the plurality of second word lines, each of the plurality of first word lines covering the first semiconductor layer in the active pillar corresponding to the first word line, and each of the plurality of second word lines covering the third semiconductor layer in the active pillar corresponding to the second word line;
- and
- a plurality of third word lines and a plurality of fourth word lines, the plurality of third word lines and the plurality of fourth word lines extending in the third direction, each column of the active pillars arranged in the third direction corresponding to a respective one of the plurality of third word lines and a respective one of the plurality of fourth word lines, each of the plurality of third word lines covering the first semiconductor layer in the active pillar corresponding to the third word line, each of the plurality of fourth word lines covering the third semiconductor layer in the active pillar corresponding to the fourth word line, the plurality of third word lines and the plurality of first word lines being spaced apart in the first direction, and the plurality of fourth word lines and the plurality of second word lines being spaced apart in the first direction;
- wherein each of the plurality of active pillars sequentially comprises a first doped region, a first channel region, a co-doped region, a second channel region and a second doped region in the first direction, the first channel region and the second channel region are respectively covered by a second word line in the plurality of second word lines and a fourth word line in the plurality of fourth word lines the first doped region, the first channel region, the co-doped region and the second word line constitute a first transistor, the co-doped region, the second channel region, the second doped region and the fourth word line constitute a second transistor, the co-doped region serves as a common source/drain of the first transistor and the second transistor, and the first doped region and the second doped region serve as a drain/source of the first transistor and a drain/source of the second transistor, respectively.