US 12,506,798 B2Granted

Network interface device

AssigneeXilinx, Inc.

InventorsSteven L. Pope, Derek Roberts, David J. Riddoch

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Abstract

A network interface device having an FPGA for providing an FPGA application. A first interface between a host computing device and the FPGA application is provided, allowing the FPGA application to make use of data-path operations provided by a transport engine on the network interface device, as well as communicate with the host. The FPGA application sends and receives data with the host via a memory that is memory mapped to a shared memory location in the host computing device, whilst the transport engine sends and receives data packets with the host via a second memory. A second interface is provided to interface the FPGA application and transport engine with the network, wherein the second interface is configured to back-pressure the transport engine.

Claims20

Dependent claims

A network interface device arranged to couple a host computing device to a network, said network interface device comprising:

a first interface configured to receive data from the host computing device;
a programmable circuit providing a first application;
and
transport processing circuitry for performing transport protocol processing of data for transmission over the network, the transport processing circuitry being separate to the programmable circuit,
wherein the first interface is configured to:
direct a first part of the data received from the host to the first application prior to the first part of the data being directed to the transport processing circuitry, and
direct a second part of the data received from the host to the transport processing circuitry;
wherein the first application is configured to (i) perform application processing of the first part of the data and (ii) after processing of the first part of the data, pass the application-processed first part of the data to the transport processing circuitry for transport protocol processing and network transmission;
and
wherein the transport processing circuitry is configured to:
perform the transport protocol processing of the first part of the data after the application processing of the first part of the data by the first application, and
perform the transport protocol processing of the second part of the data, wherein the second part of the data bypasses the application processing by the first application.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/867,656Filed 18 Jul 2022 · continuation
Priority: 19 Dec 2017
Published: US 2022/0400147 A115 Dec 2022
Granted: 23 Dec 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H04L 67/10
Protocols: in which an application is distributed across nodes in the network
G06F 9/5044
The resource being a machine, e.g. CPUs, Servers, Terminals: considering hardware capabilities
H04L 45/38
Routing or path finding of packets in data switching networks: flow based routing
H04L 49/30
Packet switching elements: peripheral units, e.g. input or output ports

Family

Application15/847,778Parent of this continuation · filed 19 Dec 2017
Application16/874,594Parent of this continuation · filed 14 May 2020
US 10,686,872 B2Parent of this continuation · filed 16 Jun 2020
US 2022/0400147 A1Pre-grant publication · published 15 Dec 2022
US 11,394,768 B2Parent of this continuation
US 2019/0190982 A1Published application
US 2020/0274921 A1Published application
US 12,506,798 B2This patent

From the US filing history. Foreign family members aren’t listed.