US 12,506,648 B2 · Signal processing device and associated signal processing method

Abstract

A signal processing device includes a proprietary test mode symbol generating circuit, a decision error detection circuit, and a debug control circuit. The proprietary test mode symbol generating circuit generates prediction symbols as a reference signal according to decision symbols output by a slicer of a receiving signal processing circuit and a predetermined rule. The decision error detection circuit operating in a proprietary test mode continues receiving the decision symbols and the prediction symbols, and generates detection results. The debug control circuit includes a memory device, and continues recording contents of one or more signals obtained from one or more nodes of the receiving signal processing circuit into the memory device. In addition, the debug control circuit receives the detection results, and stops recording the contents of the one or more signals in response to a state of at least one of the detection results.

Claims10

Dependent claims

A signal processing device, comprising:

a proprietary test mode symbol generating circuit, coupled to a receiving signal processing circuit, and arranged to generate multiple prediction symbols as a reference signal according to multiple decision symbols output by a slicer of the receiving signal processing circuit and a predetermined rule;
a decision error detection circuit, operating in a proprietary test mode, and arranged to continue receiving the multiple decision symbols and the multiple prediction symbols, and generate multiple detection results;
and
a debug control circuit, coupled to one or more nodes of the receiving signal processing circuit, comprising a memory device, and arranged to continue recording contents of one or more signals obtained from the one or more nodes into the memory device,
wherein the debug control circuit receives the multiple detection results, and stops recording the contents of the one or more signals in response to a state of at least one of the multiple detection results.

2 more elements

A signal processing method, arranged to process signals received by a receiver within a communication system, wherein the receiver comprises a receiving signal processing circuit, the receiving signal processing circuit operates in a data exchange phase after parameter training of a decision feedback equalizer of the receiving signal processing circuit has been completed, wherein the signal processing method comprises:

determining, by a mode control circuit, whether to enter a proprietary test mode during the data exchange phase in response to a value of a register;
generating, by a proprietary test mode symbol generating circuit, multiple prediction symbols as a reference signal according to multiple decision symbols output by a slicer of the receiving signal processing circuit and a predetermined rule;
continuing receiving and detecting, by a decision error detection circuit, the multiple decision symbols and the multiple prediction symbols, and generating multiple detection results;
continuing obtaining and recording, by a debug control circuit, contents of one or more signals obtained from one or more nodes of the receiving signal processing circuit;
and
stopping recording, by the debug control circuit, the contents of the one or more signals in response to a state of at least one of the multiple detection results.

3 more elements

Dependencies are inferred from the claim text.

Signal processing device and associated signal processing method

Life of this patent

Signal processing device and associated signal processing method

Life of this patent

Abstract

Claims10