Failure analysis and location method for short circuit structure

A failure analysis and location method for a short circuit structure, at least comprising:

• step 1, providing a semiconductor structure, the semiconductor structure comprising:
• a first layer metal wire structure and a second layer metal wire structure located above the first layer metal wire structure, wherein the first layer metal wire structure and the second layer metal wire structure are connected by a first layer metal via located between the first layer metal wire structure and the second layer metal wire structure;
• and a second layer metal via located above the second layer metal wire structure and connected to the second layer metal wire structure;
• step 2, roughly locating a voltage contrast (VC) anomaly in the semiconductor structure to find a failure region;
• step 3, plating the failure region with a conductive material layer to connect the second layer metal via to the conductive material layer;
• step 4, performing focused ion beam sample preparation along the failure region to form a sample, and observing a VC on a cross-section of the sample, wherein when an abnormal VC is found at a position on the cross-section of the sample, a failure point at the position is accurately located;
• and
• step 5, representing a morphology of the failure point, and analyzing a failure mechanism.