Discharge circuits for a NAND flash memory
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsWeiwei He, Liang Qiao, Mingxian Lei
Life of this patent
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Abstract
A method of operating a memory device is disclosed. The memory device includes a memory string coupled with a bit line and a common source line. An erase voltage is applied to the bit line and the common source line in an erase operation. The bit line and the common source line are discharged in a discharge operation after the erase operation. A voltage difference between the bit line and the common source line is less than a first predetermined value during a period of the discharge operation.
Claims20
A method of operating a memory device, wherein the memory device comprises a memory string coupled with a bit line and a common source line, the method comprising:
- applying an erase voltage to the bit line and the common source line in an erase operation;
- and
- discharging the bit line and the common source line in a discharge operation after the erase operation, wherein a voltage difference between the bit line and the common source line is less than a first predetermined value during a period of the discharge operation.
A memory device, comprising:
- a memory block, comprising memory strings connected to a common source line and bit lines;
- and
- a peripheral circuit comprising discharge transistors, each of the discharge transistors connected between the common source line and a corresponding bit line, wherein the peripheral circuit is configured to:
- apply an erase voltage to the common source line and the bit lines in an erase operation;
- and
- discharge the bit lines and the common source line in a discharge operation after the erase operation, wherein a voltage difference between the bit lines and the common source line is less than a first predetermined value during a period of the discharge operation.
A memory system, comprising:
- a memory device, comprising:
- a memory block, comprising memory strings connected to a common source line and bit lines;
- and
- a peripheral circuit comprising discharge transistors, each of the discharge transistors connected between the common source line and a corresponding bit line, wherein the peripheral circuit is configured to:
- apply an erase voltage to the common source line and the bit lines in an erase operation;
- and
- discharge the bit lines and the common source line in a discharge operation after the erase operation, wherein a voltage difference between the bit lines and the common source line is less than a first predetermined value during a period of the discharge operation;
- and
- a memory controller configured to manage the memory device through a memory channel.
Dependencies are inferred from the claim text.