Asynchronous read circuit using delay sensing in magnetoresistive random access memory (MRAM)

A memory device, comprising:

• an active data path including a memory element;
• reference data path including a reference memory element, the reference memory element having a resistance that differs from a resistance of the memory element;
• and
• a delay-sensing element having a first input coupled to the active data path and a second input coupled to the reference data path;
• wherein the delay-sensing element comprises:
• a first NAND gate having a first first NAND gate input coupled to the active data path, a second first NAND gate input coupled to a second NAND gate output, and a first NAND gate output;
• a second NAND gate having a first second NAND gate input coupled to the first NAND gate output, a second second NAND gate input coupled to the reference data path, and the second NAND gate output;
• a third NAND gate having a first third NAND gate input coupled to the first NAND gate output, a second third NAND gate input coupled to a fourth NAND gate output, and a third NAND gate output;
• and
• a fourth NAND gate having a first fourth NAND gate input coupled to the third NAND gate output, a second fourth NAND gate input coupled to the second NAND gate output, and the fourth NAND gate output.