US 12,505,066 B2Granted

Execution state management

AssigneeSambaNova Systems, Inc.

InventorsKin Hing Leung, Manish K. Shah, Ram Sivaramakrishnan, Raghu Prabhakar

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Abstract

A system includes a first coarse-grained reconfigurable (CGR) processor including first and second CGR arrays. A second CGR processor includes third and fourth CGR arrays. Each CGR array includes an address generator and coalescing unit (AGCU) designated as an array master AGCU (AMAGCU). The first CGR array AGCU is also designated as a processor master AGCU (PMAGCU) and as a system master (SMAGCU). The third CGR array AGCU is also designated as a PMAGCU. Each AMAGCU performs first execution synchronization actions, each PMAGCU also performs second execution synchronization actions, and the SMAGCU also performs third execution synchronization actions. The execution synchronization actions include a token exchange protocol for tokens such as “array ready”, “processor ready”, “system master ready”, “program start”, “array done, “processor done”, and “program terminate”. The tokens are communicated over a token bus via token interfaces that include a bus interface and a token receive FIFO.

Claims15

Dependent claims

A coarse-grained reconfigurable processor (a CGR processor) including one or more physical CGR arrays, wherein each physical CGR array includes an array of CGR units, an address generator and coalescing unit (AGCU), and a token interface, wherein:

the token interface includes a bus interface, a token receive first-in-first-out memory (a token receive FIFO) coupled between the bus interface and the AGCU, and a token transmit FIFO coupled between the AGCU and the bus interface;
the token interface is configured to communicate with another token interface via a token bus;
the token interface is operable to receive tokens from the token bus and store received tokens in its token receive FIFO independent of a readiness of the array of CGR units and a readiness of the AGCU;
and
the AGCU is operable to:
load and unload configuration data into and out of the array of CGR units;
determine a configuration data load status and transmit a token including the configuration data load status via the token interface and the token bus;
receive a program start token, and in response to receiving the program start token, start program execution in the array of CGR units;
and
receive a program termination token, and in response to receiving the program termination token, terminate program execution in the array of CGR units.

7 more elements

A system comprising at least a first CGR processor, wherein:

the first CGR processor is configured with first configuration data that causes the first CGR processor to execute at least a first part of a computation graph included in at least a first part of a logical CGR array mapped to multiple physical CGR arrays, and to execute a synchronization protocol including actions to synchronize execution of the first part of the computation graph with execution of a second part of the computation graph;
wherein:
the synchronization protocol includes an execution start synchronization protocol and an execution termination synchronization protocol;
and
an AGCU of a first physical CGR array of the multiple physical CGR arrays mapped to the logical CGR array is configured with second configuration data to act as a system master AGCU (an SMAGCU) and to implement at least a first part of the execution start synchronization protocol and at least a first part of the execution termination synchronization protocol for the multiple physical CGR arrays.

2 more elements

A method for synchronizing a system including one or more CGR processors each including one or more physical CGR arrays that jointly execute a computation graph, comprising:

receiving the computation graph and partitioning the computation graph into partitions;
assigning the partitions to parts of a logical CGR array;
mapping the parts of the logical CGR array to at least a part of the one or more physical CGR arrays;
designating one AGCU in each of the one or more physical CGR arrays mapped to the partitions as an AMAGCU;
for each of the one or more CGR processors, designating one AGCU in a physical CGR array that is mapped to a partition as a PMAGCU;
for one of the one or more physical CGR arrays that are mapped to partitions, designating one AGCU as an SMAGCU;
configuring the SMAGCU for performing a first part of actions in a synchronization protocol;
configuring each PMAGCU for performing a second part of actions in the synchronization protocol;
configuring each AMAGCU for performing a third part of actions in the synchronization protocol;
upon completion of configuring each AMAGCU, sending an “array ready” token from the AMAGCU to the PMAGCU;
upon completion of configuring each PMAGCU and receiving “array ready” tokens from AMAGCUs, sending a “processor ready” token from the PMAGCU to the SMAGCU;
upon completion of configuring the SMAGCU and receiving a “processor ready” token from each PMAGCU, broadcasting a “program start” token from the SMAGCU;
executing the computation graph in the one or more physical CGR arrays;
from AMAGCU, upon completion of a final task, sending a token “array done” to the PMAGCU;
from each PMAGCU in one of the one or more CGR processors, upon receiving “array done” tokens from all AMAGCUs in the one of the one or more CGR processors, sending a token “processor done” to the SMAGCU;
and
in the SMAGCU, upon receiving a “processor done” token from each PMAGCU in the one or more CGR processors, broadcasting a “program terminate” token.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/978,937Filed 1 Nov 2022 · us provisional application
Priority: 1 Nov 2021
Published: US 2023/0134744 A14 May 2023
Granted: 23 Dec 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 9/522
Program synchronisation; Mutual exclusion, e.g. by means of semaphores: barrier synchronisation
G06F 15/17325
Intercommunication techniques: synchronisation; Hardware support therefor
G06F 15/7867
Comprising a single central processing unit: with reconfigurable architecture
G06F 15/7871
With reconfigurable architecture: reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS