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US 12,505,065 B2Granted
On-package die-to-die (D2D) interconnect for memory using universal chiplet interconnect express (UCIe) PHY
AssigneeIntel Corporation
InventorsDebendra Das Sharma, Narasimha Lanka, Peter Onufryk, Swadesh Choudhary, Gerald Pasdast, Zuoguo Wu, Dimitrios Ziakas, Sridhar Muthrasanallur
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Abstract
Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to on-package die-to-die (D2D) interconnects. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.
Claims20
An apparatus, comprising:
- a system-on-a-chip (SoC) comprising an integrated circuit on a semiconductor die, the SoC comprising a memory controller and a universal chiplet interconnect express (UCIe) interface for a UCIe interconnect, the UCle interface comprising interface logic to manage transport of data over the UCIe interconnect in a transmit mode, the interface logic to:
- decode memory signals from the memory controller;
- map the memory signals to UCle signals;
- and
- encode the UCle signals for transmission over a transmit channel of the UCle interconnect.
2 more elements
An apparatus, comprising:
- a system-on-a-chip (SoC) fabric of a SoC comprising an integrated circuit on a semiconductor die, the SoC fabric comprising a universal chiplet interconnect express (UCIe) interface for a UCIe interconnect, the UCle interface comprising interface logic to manage transport of data over the UCle interconnect in a transmit mode, the interface logic to:
- decode memory signals from over the SoC fabric;
- map the memory signals to UCle signals;
- and
- encode the UCle signals for transmission over an asymmetric link of the UCle interconnect.
2 more elements
A method, comprising:
- decoding memory signals from a memory controller of a system-on-a-chip (SoC) comprising an integrated circuit on a semiconductor die, the SoC comprising the memory controller and a universal chiplet interconnect express (UCle) interface for a UCIe interconnect, the UCle interface comprising interface logic to manage transport of data over the UCIe interconnect in a transmit mode;
- mapping the memory signals to UCle signals;
- and
- encoding the UCle signals for transmission over a transmit channel of the UCle interconnect.
1 more element
Dependencies are inferred from the claim text.