DRAM ECC circuit error detection integrity

A dynamic random-access memory (DRAM) comprising:

• a DRAM core;
• and
• an error correction code (ECC) engine, the DRAM communicating with a system-on-chip (SoC) to:
• calculate, using the DRAM, parity bits for first write data;
• store the first write data and the parity bits in a DRAM core of the DRAM;
• store second write data in the DRAM core without calculating parity bits for the second write data;
• enable the DRAM to calculate the parity bits of the second write data and compare the parity bits of the second write data to the parity bits of the first write data;
• and
• calculate a syndrome based on a comparison between the parity bits of the second write data and the parity bits of the first write data to correct errors detected in the DRAM core.

A method comprising:

• calculating, using a dynamic random-access memory (DRAM), parity bits for first write data;
• storing the first write data and the parity bits in a DRAM core of the DRAM;
• storing second write data in the DRAM core without calculating parity bits for the second write data;
• enabling the DRAM to calculate the parity bits of the second write data and compare the parity bits of the second write data to the parity bits of the first write data;
• and
• calculating a syndrome based on a comparison between the parity bits of the second write data and the parity bits of the first write data to correct errors detected in the DRAM core.