Asynchronous state machine for a switching converter
AssigneeSTMicroelectronics International N.V.
InventorDavid Chesneau
Life of this patent
Estimating the term…
Abstract
An asynchronous finite state machine has states coupled by transitions each implemented by a flip-flop. Each flip-flop supplies a bit of a state of arrival of the corresponding transition, and receives a bit of an initial state of this transition on its data input and a first signal dedicated to the flip-flop on its control input. A circuit supplies, for each transition, a second signal of request for the transition. Another circuit generates based on the second signals, at each request for a transition and in the absence of a pulse of the first signals, a pulse of the first signal dedicated to the flip-flop of this transition, and a pulse of the first signal dedicated to each flip-flop supplying a bit to the flip-flop of the transition.
Claims22
An asynchronous finite state machine for controlling high-side and low-side switches of a switching converter, wherein the asynchronus finite state machine comprises a plurality of states connected together by transitions, comprising:
- a flip-flop implementing each transition, wherein each flip-flop has an output configured to supply a bit representative of a state of the asynchronous finite state machine, said state being a state of arrival of the transition implemented by the flip-flop, a data input configured to receive a bit representative of an initial state of the transition implemented by the flip-flop, and a control input configured to receive a first binary signal dedicated to said flip-flop;
- a first combinational circuit is configured to supply, based on input signals of the asynchronous finite state machine and on the bits supplied by the outputs of the flip-flops, and for each transition, a second binary signal corresponding to said transition and indicating whether an implementation of said transition is required or not;
- and
- a second circuit is configured to generate based on the second binary signals, at each request of implementation of a transition and in the absence of a pulse of the first binary signals, a pulse of the first binary signal dedicated to the flip-flop implementing said transition, and a pulse of the first binary signal dedicated to each flip-flop having its output configured to supply a bit to the data input of the flip-flop implementing said transition.
An asynchronous finite state machine having a plurality of states connected together by transitions, comprising:
- a flip-flop for each transition, wherein an output of each flip-flop supplies a bit representative of an arrival state of the asynchronous finite state machine, wherein a data input receives a bit representative of an initial state of the transition, and a control input receives a first binary signal dedicated to said flip-flop;
- a first combinational circuit configured to process input signals of the asynchronous finite state machine and the bits at the outputs of the flip-flops to generate, for each transition, a second binary signal indicating an implementation of said transition;
- and
- a second circuit is configured to process the second binary signals and, for each implementation of a transition, generate a pulse of the first binary signal dedicated to the flip-flop implementing said transition and generate a pulse of the first binary signal dedicated to each flip-flop whose output supplies a bit to the data input of said flip-flop implementing said transition.
Dependencies are inferred from the claim text.