Power down of memory device based on hardware reset signal
AssigneeMicron Technology, Inc.
InventorsGianluca Coppola, Steffen Buch
Life of this patent
Estimating the term…
Abstract
In some implementations, a memory device may receive, from a host device, a hardware reset signal. The memory device may determine that a level associated with the hardware reset signal satisfies a threshold for a period of time. The memory device may determine, based on the hardware reset signal satisfying the threshold for the period of time, that the host device is expected to power down the memory device. The memory device may complete an ongoing memory operation within a remaining time period based on the determination that the host device is expected to power down the memory device.
Claims20
A memory device, comprising:
- one or more components configured to:
- set a power on time to a field in a register of the memory device based on an estimated amount of time to complete memory operations after being notified that a host device is going to power down the memory device;
- communicate, to the host device, the field;
- receive, from the host device, a hardware reset signal;
- determine that a level associated with the hardware reset signal satisfies a threshold for a period of time;
- determine, based on the hardware reset signal satisfying the threshold for the period of time, that the host device is expected to power down the memory device;
- and
- complete an ongoing memory operation within the power on time based on the determination that the host device is expected to power down the memory device.
A method, comprising:
- setting, by a memory device, a power on time to a field in a register of the memory device based on an estimated amount of time to complete memory operations after being notified that a host device is going to power down the memory device;
- communicating, from the memory device to the host device, the field;
- receiving, by the memory device from the host device, a hardware reset signal;
- determining, by the memory device, that the hardware reset signal corresponds to a predefined pattern;
- determining, by the memory device and based on the hardware reset signal corresponding to the predefined pattern, that the host device is expected to power down the memory device;
- and
- completing, by the memory device, an ongoing memory operation within the power on time based on the determining that the host device is expected to power down the memory device.
A system, comprising:
- a host device configured to:
- provide a hardware reset signal at a level that satisfies a threshold for a period of time, wherein the hardware reset signal is provided based on an expected power down of a memory device;
- and
- the memory device configured to:
- set a power on time to a field in a register of the memory device based on an estimated amount of time to complete memory operations after being notified that the host device is going to power down the memory device;
- communicate, to the host device, the field;
- receive the hardware reset signal from the host device;
- determine that the level associated with the hardware reset signal satisfies the threshold for a period of time;
- determine, based on the hardware reset signal satisfying the threshold for the period of time, that the host device is expected to power down the memory device;
- and
- complete any ongoing memory operations within the power on time based on the determination that the host device is expected to power down the memory device.
Dependencies are inferred from the claim text.